[AArch64] Teach getTestBitOperand to look through ANY_EXTENDS

[craig.topper]

Summary

This patch teach getTestBitOperand to look through ANY_EXTENDs when the extended bits aren't used. The test case changed here is based what D60358 did to test16 in tbz-tbnz.ll. So this patch will avoid that regression.

[spatel]

LGTM

llvm/test/CodeGen/AArch64/tbz-tbnz.ll

371

As usual, I prefer to see positive (and complete and auto-generated) checks. The script can take a function name argument if updating this whole file is too painful.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
 
   // (tbz (trunc x), b) -> (tbz x, b)
   // This case is just here to enable more of the below cases to be caught.
   if (Op->getOpcode() == ISD::TRUNCATE &&
       Bit < Op->getValueType(0).getSizeInBits()) {
     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
   }
 
+  // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
+  if (Op->getOpcode() == ISD::ANY_EXTEND &&
+      Bit < Op->getOperand(0).getValueSizeInBits()) {
+    return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
+  }
+
   if (Op->getNumOperands() != 2)
     return Op;
 
   auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
   if (!C)
     return Op;
 
   switch (Op->getOpcode()) {

llvm/test/CodeGen/AArch64/tbz-tbnz.ll

 define void @test20(i32 %in) {
 ; CHECK-LABEL: @test20
   %shl = shl i32 %in, 3
   %zext = zext i32 %shl to i64
   %and = and i64 %zext, 32
   %cond = icmp eq i64 %and, 0
   br i1 %cond, label %then, label %end
 
-; FIXME: Should be no lsl
-; CHECK: lsl w8, w0, #3
-; CHECK: tbnz w8, #5
+; CHECK-NOT: lsl
+; CHECK: tbnz w0, #2
 
 then:
   call void @t()
   br label %end
 
 end:
   ret void
 }