Page MenuHomePhabricator

[x86] make 8-bit shl undesirable
ClosedPublic

Authored by spatel on Apr 4 2019, 2:34 PM.

Details

Summary

I was looking at a potential DAGCombiner fix for 1 of the regressions in D60278, and it caused severe regression test pain because x86 TLI lies about the desirability of 8-bit shift ops.

We've hinted at making all 8-bit ops undesirable for the reason in the code comment:

// TODO: Almost no 8-bit ops are desirable because they have no actual
//       size/speed advantages vs. 32-bit ops, but they do have a major
//       potential disadvantage by causing partial register stalls.

...but that leads to massive diffs and exposes all kinds of optimization holes itself. So I'm trying for 1 tiny opcode step at a time. :)

Diff Detail

Repository
rL LLVM

Event Timeline

spatel created this revision.Apr 4 2019, 2:34 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 4 2019, 2:34 PM
andreadb accepted this revision.Apr 5 2019, 3:24 AM

Looks good to me.

This revision is now accepted and ready to land.Apr 5 2019, 3:24 AM

Little steps..... LGTM (@andreadb any comments?)

craig.topper added inline comments.Apr 5 2019, 1:54 PM
llvm/test/CodeGen/X86/scheduler-backtracking.ll
19 ↗(On Diff #193786)

We should get this down to addl %esi, %esi.

Closed by commit rL357912: [x86] make 8-bit shl undesirable (authored by spatel, committed by ). · Explain WhyApr 8 2019, 7:01 AM
This revision was automatically updated to reflect the committed changes.