[AArch64] Add lowering pattern for scalar fp16 facge and facgt

[dnsampaio]

Summary

The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands.

[javed.absar]

test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll

324

move the declares to the top like the rest of the tests.

328

fix/alignindentation

[dnsampaio]

Attended requests.

[dnsampaio]

Ping.
I know the usual time is a week, but for such a small bug-fix I don't believe much more people would care.

lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)),
             (i32 (IMPLICIT_DEF)),
             (FCVTZUh FPR16:$Rn, vecshiftR32:$imm),
             hsub))>;
 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)),
           (i64 (INSERT_SUBREG
             (i64 (IMPLICIT_DEF)),
             (FCVTZUh FPR16:$Rn, vecshiftR64:$imm),
             hsub))>;
+def : Pat<(i32 (int_aarch64_neon_facge (f16 FPR16:$Rn), (f16 FPR16:$Rm))),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FACGE16 FPR16:$Rn, FPR16:$Rm),
+            hsub))>;
+def : Pat<(i32 (int_aarch64_neon_facgt (f16 FPR16:$Rn), (f16 FPR16:$Rm))),
+          (i32 (INSERT_SUBREG
+            (i32 (IMPLICIT_DEF)),
+            (FACGT16 FPR16:$Rn, FPR16:$Rm),
+            hsub))>;
 
 defm SHL      : SIMDScalarLShiftD<   0, 0b01010, "shl", AArch64vshl>;
 defm SLI      : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
 defm SQRSHRN  : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
                                      int_aarch64_neon_sqrshrn>;
 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
                                      int_aarch64_neon_sqrshrun>;
 defm SQSHLU   : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;

test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll

 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16  | FileCheck %s
 
 declare half @llvm.aarch64.sisd.fabd.f16(half, half)
 declare half @llvm.aarch64.neon.fmax.f16(half, half)
 declare half @llvm.aarch64.neon.fmin.f16(half, half)
 declare half @llvm.aarch64.neon.frsqrts.f16(half, half)
 declare half @llvm.aarch64.neon.frecps.f16(half, half)
 declare half @llvm.aarch64.neon.fmulx.f16(half, half)
 declare half @llvm.fabs.f16(half)
+declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half)
+declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half)
 
 define dso_local half @t_vabdh_f16(half %a, half %b) {
 ; CHECK-LABEL: t_vabdh_f16:
 ; CHECK:         fabd h0, h0, h1
 ; CHECK-NEXT:    ret
 entry:
   %vabdh_f16 = tail call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)
   ret half %vabdh_f16

 ; CHECK-LABEL: test_vcvth_n_u32_f16_16:
 ; CHECK:         fcvtzu h0, h0, #16
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 entry:
   %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)
   ret i32 %vcvth_n_u32_f16
 }
+
+define dso_local i16 @vcageh_f16_test(half %a, half %b) {
+; CHECK-LABEL: vcageh_f16_test:
+; CHECK:        facge   h0, h0, h1
+; CHECK-NEXT:   fmov    w0, s0
+; CHECK-NEXT:   ret
+entry:
+  %facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b)
+  %0 = trunc i32 %facg to i16
+  ret i16 %0
+}
+
+define dso_local i16 @vcagth_f16_test(half %a, half %b) {
+; CHECK-LABEL: vcagth_f16_test:
+; CHECK:        facgt   h0, h0, h1
+; CHECK-NEXT:   fmov    w0, s0
+; CHECK-NEXT:   ret
+entry:
+  %facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)
+  %0 = trunc i32 %facg to i16
+  ret i16 %0
+}