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Differential D60156

[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2
ClosedPublic

Authored by craig.topper on Apr 2 2019, 3:04 PM.

Details

Reviewers
efriedma
RKSimon
spatel
reames
jfb
Commits
rG1c2dfc31005d: [X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87…
rL358211: [X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87…
Summary

If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integer and store it to a stack temporary. From there we can do two 32-bit loads to get the value into integer registers without worrying about atomicness.

This matches what gcc and icc do for this case and removes an existing FIXME.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Apr 2 2019, 3:04 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 2 2019, 3:04 PM
Herald added subscribers: dexonsmith, hiraditya. · View Herald Transcript
craig.topper marked an inline comment as done.Apr 2 2019, 3:05 PM
craig.topper added inline comments.
llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
52 ↗(On Diff #193370)

this test seemed to be testing somethign about the cmpxchg sequence so I've added noimplicitfloat to prevent the new code from triggering.

reames added a comment.Apr 3 2019, 9:17 AM

Minor comments only. I'll leave approval to someone more familiar w/x87 if possible

llvm/lib/Target/X86/X86ISelLowering.cpp
27434 ↗(On Diff #193370)

You should add a test for a volatile atomic load. Your code is correct for this case, but it doesn't appear tested.

27440 ↗(On Diff #193370)

The fact that this store *isn't* atomic or volatile deserves a comment.

llvm/test/CodeGen/X86/atomic-non-integer.ll
232 ↗(On Diff #193370)

If I'm understanding this sequence correctly - not sure I am - it looks like we could simply load directly from your inserted stack temporary instead of shuffling into another and then loading. Might be worth a TODO

craig.topper updated this revision to Diff 193575.Apr 3 2019, 1:03 PM

Add volatile atomic test case.
Add comment about the stack tempoary access not being atomic
Add FIXME for the case where we are already doing a store.

RKSimon added inline comments.Apr 9 2019, 1:13 AM
llvm/lib/Target/X86/X86ISelLowering.cpp
27431 ↗(On Diff #193575)

Do we?

craig.topper marked an inline comment as done.Apr 9 2019, 12:12 PM
craig.topper added inline comments.
llvm/lib/Target/X86/X86ISelLowering.cpp
27431 ↗(On Diff #193575)

I based that on the similar sequence in X86TargetLowering::BuildFILD. Wasn't sure if the FIXME there was still relevant.

craig.topper updated this revision to Diff 194386.Apr 9 2019, 1:21 PM

Rebase due to test file splitting.

Add coment on the glue FIXME pointing to the FIXME in BuildFILD

RKSimon accepted this revision.Apr 11 2019, 3:29 AM

LGTM

llvm/test/CodeGen/X86/atomic-load-store-wide.ll
121 ↗(On Diff #194386)

pre-commit this?

This revision is now accepted and ready to land.Apr 11 2019, 3:29 AM
Closed by commit rL358211: [X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87… (authored by ctopper). · Explain WhyApr 11 2019, 11:39 AM
This revision was automatically updated to reflect the committed changes.
Diffusion mentioned this in rL358210: [X86] Pre-commit i64 volatile test case for D60156. NFC.
craig.topper mentioned this in rG1fe5a9963de6: [X86] Pre-commit i64 volatile test case for D60156. NFC.Apr 11 2019, 11:39 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
12 lines
70 lines
13 lines
test/
CodeGen/
X86/
65 lines
58 lines
431 lines
54 lines
2 lines

Diff 194727

llvm/trunk/lib/Target/X86/X86ISelLowering.h

Show First 20 Lines • Show All 602 Lines • ▼ Show 20 Lines enum NodeType : unsigned {
/// This instruction implements SINT_TO_FP with the /// This instruction implements SINT_TO_FP with the
/// integer source in memory and FP reg result. This corresponds to the /// integer source in memory and FP reg result. This corresponds to the
/// X86::FILD*m instructions. It has two inputs (token chain and address) /// X86::FILD*m instructions. It has two inputs (token chain and address)
/// and two outputs (FP value and token chain). FILD_FLAG also produces a /// and two outputs (FP value and token chain). FILD_FLAG also produces a
/// flag). The integer source type is specified by the memory VT. /// flag). The integer source type is specified by the memory VT.
FILD, FILD,
FILD_FLAG, FILD_FLAG,
/// This instruction implements a fp->int store from FP stack
/// slots. This corresponds to the fist instruction. It takes a
/// chain operand, value to store, address, and glue. The memory VT
/// specifies the type to store as.
FIST,
/// This instruction implements an extending load to FP stack slots. /// This instruction implements an extending load to FP stack slots.
/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
/// operand, and ptr to load from. The memory VT specifies the type to /// operand, and ptr to load from. The memory VT specifies the type to
/// load from. /// load from.
FLD, FLD,
/// This instruction implements a truncating store to FP stack /// This instruction implements a truncating store from FP stack
/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
/// chain operand, value to store, and address. The memory VT specifies /// chain operand, value to store, address, and glue. The memory VT
/// the type to store as. /// specifies the type to store as.
FST, FST,
/// This instruction grabs the address of the next argument /// This instruction grabs the address of the next argument
/// from a va_list. (reads and modifies the va_list in memory) /// from a va_list. (reads and modifies the va_list in memory)
VAARG_64, VAARG_64,
// Vector truncating store with unsigned/signed saturation // Vector truncating store with unsigned/signed saturation
VTRUNCSTOREUS, VTRUNCSTORES, VTRUNCSTOREUS, VTRUNCSTORES,
▲ Show 20 Lines • Show All 983 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 25,578 Lines • ▼ Show 20 Lines
} }
bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
return needsCmpXchgNb(SI->getValueOperand()->getType()); return needsCmpXchgNb(SI->getValueOperand()->getType());
} }
// Note: this turns large loads into lock cmpxchg8b/16b. // Note: this turns large loads into lock cmpxchg8b/16b.
// TODO: In 32-bit mode, use MOVLPS when SSE1 is available? // TODO: In 32-bit mode, use MOVLPS when SSE1 is available?
// TODO: In 32-bit mode, use FILD/FISTP when X87 is available?
TargetLowering::AtomicExpansionKind TargetLowering::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
Type *MemType = LI->getType(); Type *MemType = LI->getType();
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we // If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
// can use movq to do the load. // can use movq to do the load. If we have X87 we can load into an 80-bit
// X87 register and store it to a stack temporary.
bool NoImplicitFloatOps = bool NoImplicitFloatOps =
LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat); LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() && if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
!Subtarget.useSoftFloat() && !NoImplicitFloatOps && Subtarget.hasSSE2()) !Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
(Subtarget.hasSSE2() || Subtarget.hasX87()))
return AtomicExpansionKind::None; return AtomicExpansionKind::None;
return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
: AtomicExpansionKind::None; : AtomicExpansionKind::None;
} }
TargetLowering::AtomicExpansionKind TargetLowering::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
▲ Show 20 Lines • Show All 1,829 Lines • ▼ Show 20 Lines case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
Results.push_back(EFLAGS.getValue(1)); Results.push_back(EFLAGS.getValue(1));
return; return;
} }
case ISD::ATOMIC_LOAD: { case ISD::ATOMIC_LOAD: {
assert(N->getValueType(0) == MVT::i64 && "Unexpected VT!"); assert(N->getValueType(0) == MVT::i64 && "Unexpected VT!");
bool NoImplicitFloatOps = bool NoImplicitFloatOps =
DAG.getMachineFunction().getFunction().hasFnAttribute( DAG.getMachineFunction().getFunction().hasFnAttribute(
Attribute::NoImplicitFloat); Attribute::NoImplicitFloat);
if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps && if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
Subtarget.hasSSE2()) {
auto *Node = cast<AtomicSDNode>(N); auto *Node = cast<AtomicSDNode>(N);
// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the lower if (Subtarget.hasSSE2()) {
// 64-bits. // Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the
// lower 64-bits.
SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
SDValue Ops[] = { Node->getChain(), Node->getBasePtr() }; SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
MVT::i64, Node->getMemOperand()); MVT::i64, Node->getMemOperand());
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld, SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0, dl));
Results.push_back(Res); Results.push_back(Res);
Results.push_back(Ld.getValue(1)); Results.push_back(Ld.getValue(1));
return; return;
} }
if (Subtarget.hasX87()) {
// First load this into an 80-bit X87 register. This will put the whole
// integer into the significand.
// FIXME: Do we need to glue? See FIXME comment in BuildFILD.
SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other, MVT::Glue);
SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
SDValue Result = DAG.getMemIntrinsicNode(X86ISD::FILD_FLAG,
dl, Tys, Ops, MVT::i64,
Node->getMemOperand());
SDValue Chain = Result.getValue(1);
SDValue InFlag = Result.getValue(2);
// Now store the X87 register to a stack temporary and convert to i64.
// This store is not atomic and doesn't need to be.
// FIXME: We don't need a stack temporary if the result of the load
// is already being stored. We could just directly store there.
SDValue StackPtr = DAG.CreateStackTemporary(MVT::i64);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
MachinePointerInfo MPI =
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
SDValue StoreOps[] = { Chain, Result, StackPtr, InFlag };
Chain = DAG.getMemIntrinsicNode(X86ISD::FIST, dl,
DAG.getVTList(MVT::Other), StoreOps,
MVT::i64, MPI, 0 /*Align*/,
MachineMemOperand::MOStore);
// Finally load the value back from the stack temporary and return it.
// This load is not atomic and doesn't need to be.
// This load will be further type legalized.
Result = DAG.getLoad(MVT::i64, dl, Chain, StackPtr, MPI);
Results.push_back(Result);
Results.push_back(Result.getValue(1));
return;
}
}
// TODO: Use MOVLPS when SSE1 is available? // TODO: Use MOVLPS when SSE1 is available?
// TODO: Use FILD/FISTP when X87 is available?
// Delegate to generic TypeLegalization. Situations we can really handle // Delegate to generic TypeLegalization. Situations we can really handle
// should have already been dealt with by AtomicExpandPass.cpp. // should have already been dealt with by AtomicExpandPass.cpp.
break; break;
} }
case ISD::ATOMIC_SWAP: case ISD::ATOMIC_SWAP:
case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_ADD:
case ISD::ATOMIC_LOAD_SUB: case ISD::ATOMIC_LOAD_SUB:
case ISD::ATOMIC_LOAD_AND: case ISD::ATOMIC_LOAD_AND:
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Linesconst char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::SHLD: return "X86ISD::SHLD"; case X86ISD::SHLD: return "X86ISD::SHLD";
case X86ISD::SHRD: return "X86ISD::SHRD"; case X86ISD::SHRD: return "X86ISD::SHRD";
case X86ISD::FAND: return "X86ISD::FAND"; case X86ISD::FAND: return "X86ISD::FAND";
case X86ISD::FANDN: return "X86ISD::FANDN"; case X86ISD::FANDN: return "X86ISD::FANDN";
case X86ISD::FOR: return "X86ISD::FOR"; case X86ISD::FOR: return "X86ISD::FOR";
case X86ISD::FXOR: return "X86ISD::FXOR"; case X86ISD::FXOR: return "X86ISD::FXOR";
case X86ISD::FILD: return "X86ISD::FILD"; case X86ISD::FILD: return "X86ISD::FILD";
case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
case X86ISD::FIST: return "X86ISD::FIST";
case X86ISD::FP_TO_INT_IN_MEM: return "X86ISD::FP_TO_INT_IN_MEM"; case X86ISD::FP_TO_INT_IN_MEM: return "X86ISD::FP_TO_INT_IN_MEM";
case X86ISD::FLD: return "X86ISD::FLD"; case X86ISD::FLD: return "X86ISD::FLD";
case X86ISD::FST: return "X86ISD::FST"; case X86ISD::FST: return "X86ISD::FST";
case X86ISD::CALL: return "X86ISD::CALL"; case X86ISD::CALL: return "X86ISD::CALL";
case X86ISD::BT: return "X86ISD::BT"; case X86ISD::BT: return "X86ISD::BT";
case X86ISD::CMP: return "X86ISD::CMP"; case X86ISD::CMP: return "X86ISD::CMP";
case X86ISD::COMI: return "X86ISD::COMI"; case X86ISD::COMI: return "X86ISD::COMI";
case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::UCOMI: return "X86ISD::UCOMI";
▲ Show 20 Lines • Show All 16,356 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/X86/X86InstrFPStack.td

Show All 15 Lines
// FPStack specific DAG Nodes. // FPStack specific DAG Nodes.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>,
SDTCisPtrTy<1>]>; SDTCisPtrTy<1>]>;
def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>,
SDTCisPtrTy<1>]>; SDTCisPtrTy<1>]>;
def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
[SDNPHasChain, SDNPInGlue, SDNPMayStore, [SDNPHasChain, SDNPInGlue, SDNPMayStore,
SDNPMemOperand]>; SDNPMemOperand]>;
def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
[SDNPHasChain, SDNPOutGlue, SDNPMayLoad, [SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
SDNPMemOperand]>; SDNPMemOperand]>;
def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist,
[SDNPHasChain, SDNPInGlue, SDNPMayStore,
SDNPMemOperand]>;
def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>;
def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
[SDNPHasChain, SDNPMayStore, SDNPSideEffect, [SDNPHasChain, SDNPMayStore, SDNPSideEffect,
SDNPMemOperand]>; SDNPMemOperand]>;
def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), def X86fstf32 : PatFrag<(ops node:$val, node:$ptr),
Show All 28 Lines
def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>; }]>;
def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{ def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>; }]>;
def X86fist64 : PatFrag<(ops node:$val, node:$ptr),
(X86fist node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
}]>;
def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr),
(X86fp_to_mem node:$val, node:$ptr), [{ (X86fp_to_mem node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>; }]>;
def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr),
(X86fp_to_mem node:$val, node:$ptr), [{ (X86fp_to_mem node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>; }]>;
▲ Show 20 Lines • Show All 665 Lines • ▼ Show 20 Lines
def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
// Used to conv. i64 to f64 since there isn't a SSE version. // Used to conv. i64 to f64 since there isn't a SSE version.
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>; def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>;
// Used to conv. between f80 and i64 for i64 atomic loads.
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>;
def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>;
// FP extensions map onto simple pseudo-value conversions if they are to/from // FP extensions map onto simple pseudo-value conversions if they are to/from
// the FP stack. // the FP stack.
def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
Requires<[FPStackf32]>; Requires<[FPStackf32]>;
def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
Requires<[FPStackf32]>; Requires<[FPStackf32]>;
def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
Requires<[FPStackf64]>; Requires<[FPStackf64]>;
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llvm/trunk/test/CodeGen/X86/atomic-fp.ll

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define void @fadd_64r(double* %loc, double %val) nounwind { define void @fadd_64r(double* %loc, double %val) nounwind {
; X86-NOSSE-LABEL: fadd_64r: ; X86-NOSSE-LABEL: fadd_64r:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp ; X86-NOSSE-NEXT: pushl %ebp
; X86-NOSSE-NEXT: movl %esp, %ebp ; X86-NOSSE-NEXT: movl %esp, %ebp
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: pushl %ebx
; X86-NOSSE-NEXT: pushl %esi ; X86-NOSSE-NEXT: pushl %esi
; X86-NOSSE-NEXT: andl $-8, %esp ; X86-NOSSE-NEXT: andl $-8, %esp
; X86-NOSSE-NEXT: subl $16, %esp ; X86-NOSSE-NEXT: subl $24, %esp
; X86-NOSSE-NEXT: movl 8(%ebp), %esi ; X86-NOSSE-NEXT: movl 8(%ebp), %esi
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: fildll (%esi)
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %ebx, %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi) ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: faddl 12(%ebp) ; X86-NOSSE-NEXT: faddl 12(%ebp)
; X86-NOSSE-NEXT: fstpl (%esp) ; X86-NOSSE-NEXT: fstpl (%esp)
; X86-NOSSE-NEXT: movl (%esp), %ebx ; X86-NOSSE-NEXT: movl (%esp), %ebx
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: movl (%esi), %eax ; X86-NOSSE-NEXT: movl (%esi), %eax
; X86-NOSSE-NEXT: movl 4(%esi), %edx ; X86-NOSSE-NEXT: movl 4(%esi), %edx
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
define void @fadd_64g() nounwind { define void @fadd_64g() nounwind {
; X86-NOSSE-LABEL: fadd_64g: ; X86-NOSSE-LABEL: fadd_64g:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp ; X86-NOSSE-NEXT: pushl %ebp
; X86-NOSSE-NEXT: movl %esp, %ebp ; X86-NOSSE-NEXT: movl %esp, %ebp
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: pushl %ebx
; X86-NOSSE-NEXT: andl $-8, %esp ; X86-NOSSE-NEXT: andl $-8, %esp
; X86-NOSSE-NEXT: subl $24, %esp ; X86-NOSSE-NEXT: subl $32, %esp
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: fildll glob64
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %ebx, %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: lock cmpxchg8b glob64 ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fld1 ; X86-NOSSE-NEXT: fld1
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fstpl (%esp) ; X86-NOSSE-NEXT: fstpl (%esp)
; X86-NOSSE-NEXT: movl (%esp), %ebx ; X86-NOSSE-NEXT: movl (%esp), %ebx
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: movl glob64+4, %edx ; X86-NOSSE-NEXT: movl glob64+4, %edx
; X86-NOSSE-NEXT: movl glob64, %eax ; X86-NOSSE-NEXT: movl glob64, %eax
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
define void @fadd_64imm() nounwind { define void @fadd_64imm() nounwind {
; X86-NOSSE-LABEL: fadd_64imm: ; X86-NOSSE-LABEL: fadd_64imm:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp ; X86-NOSSE-NEXT: pushl %ebp
; X86-NOSSE-NEXT: movl %esp, %ebp ; X86-NOSSE-NEXT: movl %esp, %ebp
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: pushl %ebx
; X86-NOSSE-NEXT: andl $-8, %esp ; X86-NOSSE-NEXT: andl $-8, %esp
; X86-NOSSE-NEXT: subl $24, %esp ; X86-NOSSE-NEXT: subl $32, %esp
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: fildll -559038737
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %ebx, %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: lock cmpxchg8b -559038737 ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fld1 ; X86-NOSSE-NEXT: fld1
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fstpl (%esp) ; X86-NOSSE-NEXT: fstpl (%esp)
; X86-NOSSE-NEXT: movl (%esp), %ebx ; X86-NOSSE-NEXT: movl (%esp), %ebx
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: movl -559038737, %eax ; X86-NOSSE-NEXT: movl -559038737, %eax
; X86-NOSSE-NEXT: movl -559038733, %edx ; X86-NOSSE-NEXT: movl -559038733, %edx
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
define void @fadd_64stack() nounwind { define void @fadd_64stack() nounwind {
; X86-NOSSE-LABEL: fadd_64stack: ; X86-NOSSE-LABEL: fadd_64stack:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp ; X86-NOSSE-NEXT: pushl %ebp
; X86-NOSSE-NEXT: movl %esp, %ebp ; X86-NOSSE-NEXT: movl %esp, %ebp
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: pushl %ebx
; X86-NOSSE-NEXT: andl $-8, %esp ; X86-NOSSE-NEXT: andl $-8, %esp
; X86-NOSSE-NEXT: subl $32, %esp ; X86-NOSSE-NEXT: subl $40, %esp
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: fildll (%esp)
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %ebx, %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: lock cmpxchg8b (%esp) ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fld1 ; X86-NOSSE-NEXT: fld1
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fstpl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: movl (%esp), %eax ; X86-NOSSE-NEXT: movl (%esp), %eax
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; X86-NOSSE-LABEL: fadd_array: ; X86-NOSSE-LABEL: fadd_array:
; X86-NOSSE: # %bb.0: # %bb ; X86-NOSSE: # %bb.0: # %bb
; X86-NOSSE-NEXT: pushl %ebp ; X86-NOSSE-NEXT: pushl %ebp
; X86-NOSSE-NEXT: movl %esp, %ebp ; X86-NOSSE-NEXT: movl %esp, %ebp
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: pushl %ebx
; X86-NOSSE-NEXT: pushl %edi ; X86-NOSSE-NEXT: pushl %edi
; X86-NOSSE-NEXT: pushl %esi ; X86-NOSSE-NEXT: pushl %esi
; X86-NOSSE-NEXT: andl $-8, %esp ; X86-NOSSE-NEXT: andl $-8, %esp
; X86-NOSSE-NEXT: subl $24, %esp ; X86-NOSSE-NEXT: subl $32, %esp
; X86-NOSSE-NEXT: movl 20(%ebp), %esi ; X86-NOSSE-NEXT: movl 20(%ebp), %esi
; X86-NOSSE-NEXT: movl 8(%ebp), %edi ; X86-NOSSE-NEXT: movl 8(%ebp), %edi
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: fildll (%edi,%esi,8)
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %ebx, %ebx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: lock cmpxchg8b (%edi,%esi,8) ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp) ; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: faddl 12(%ebp) ; X86-NOSSE-NEXT: faddl 12(%ebp)
; X86-NOSSE-NEXT: fstpl (%esp) ; X86-NOSSE-NEXT: fstpl (%esp)
; X86-NOSSE-NEXT: movl (%esp), %ebx ; X86-NOSSE-NEXT: movl (%esp), %ebx
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: movl (%edi,%esi,8), %eax ; X86-NOSSE-NEXT: movl (%edi,%esi,8), %eax
; X86-NOSSE-NEXT: movl 4(%edi,%esi,8), %edx ; X86-NOSSE-NEXT: movl 4(%edi,%esi,8), %edx
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/atomic-load-store-wide.ll

Show All 39 Lines
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movd %xmm0, %eax ; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: pextrd $1, %xmm0, %edx ; SSE42-NEXT: pextrd $1, %xmm0, %edx
; SSE42-NEXT: retl ; SSE42-NEXT: retl
; ;
; NOSSE-LABEL: test2: ; NOSSE-LABEL: test2:
; NOSSE: # %bb.0: ; NOSSE: # %bb.0:
; NOSSE-NEXT: pushl %ebx ; NOSSE-NEXT: pushl %ebp
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: pushl %esi ; NOSSE-NEXT: .cfi_offset %ebp, -8
; NOSSE-NEXT: .cfi_def_cfa_offset 12 ; NOSSE-NEXT: movl %esp, %ebp
; NOSSE-NEXT: .cfi_offset %esi, -12 ; NOSSE-NEXT: .cfi_def_cfa_register %ebp
; NOSSE-NEXT: .cfi_offset %ebx, -8 ; NOSSE-NEXT: andl $-8, %esp
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; NOSSE-NEXT: subl $8, %esp
; NOSSE-NEXT: xorl %eax, %eax ; NOSSE-NEXT: movl 8(%ebp), %eax
; NOSSE-NEXT: xorl %edx, %edx ; NOSSE-NEXT: fildll (%eax)
; NOSSE-NEXT: xorl %ecx, %ecx ; NOSSE-NEXT: fistpll (%esp)
; NOSSE-NEXT: xorl %ebx, %ebx ; NOSSE-NEXT: movl (%esp), %eax
; NOSSE-NEXT: lock cmpxchg8b (%esi) ; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; NOSSE-NEXT: popl %esi ; NOSSE-NEXT: movl %ebp, %esp
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: popl %ebp
; NOSSE-NEXT: popl %ebx ; NOSSE-NEXT: .cfi_def_cfa %esp, 4
; NOSSE-NEXT: .cfi_def_cfa_offset 4
; NOSSE-NEXT: retl ; NOSSE-NEXT: retl
%val = load atomic i64, i64* %ptr seq_cst, align 8 %val = load atomic i64, i64* %ptr seq_cst, align 8
ret i64 %val ret i64 %val
} }
; Same as test2, but with noimplicitfloat. ; Same as test2, but with noimplicitfloat.
define i64 @test3(i64* %ptr) noimplicitfloat { define i64 @test3(i64* %ptr) noimplicitfloat {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
Show All 25 Lines
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movd %xmm0, %eax ; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: pextrd $1, %xmm0, %edx ; SSE42-NEXT: pextrd $1, %xmm0, %edx
; SSE42-NEXT: retl ; SSE42-NEXT: retl
; ;
; NOSSE-LABEL: test4: ; NOSSE-LABEL: test4:
; NOSSE: # %bb.0: ; NOSSE: # %bb.0:
; NOSSE-NEXT: pushl %ebx ; NOSSE-NEXT: pushl %ebp
; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: pushl %esi
; NOSSE-NEXT: .cfi_def_cfa_offset 12
; NOSSE-NEXT: .cfi_offset %esi, -12
; NOSSE-NEXT: .cfi_offset %ebx, -8
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: xorl %edx, %edx
; NOSSE-NEXT: xorl %ecx, %ecx
; NOSSE-NEXT: xorl %ebx, %ebx
; NOSSE-NEXT: lock cmpxchg8b (%esi)
; NOSSE-NEXT: popl %esi
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: popl %ebx ; NOSSE-NEXT: .cfi_offset %ebp, -8
; NOSSE-NEXT: .cfi_def_cfa_offset 4 ; NOSSE-NEXT: movl %esp, %ebp
; NOSSE-NEXT: .cfi_def_cfa_register %ebp
; NOSSE-NEXT: andl $-8, %esp
; NOSSE-NEXT: subl $8, %esp
; NOSSE-NEXT: movl 8(%ebp), %eax
; NOSSE-NEXT: fildll (%eax)
; NOSSE-NEXT: fistpll (%esp)
; NOSSE-NEXT: movl (%esp), %eax
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; NOSSE-NEXT: movl %ebp, %esp
; NOSSE-NEXT: popl %ebp
; NOSSE-NEXT: .cfi_def_cfa %esp, 4
; NOSSE-NEXT: retl ; NOSSE-NEXT: retl
%val = load atomic volatile i64, i64* %ptr seq_cst, align 8 %val = load atomic volatile i64, i64* %ptr seq_cst, align 8
ret i64 %val ret i64 %val
} }

llvm/trunk/test/CodeGen/X86/atomic-mi.ll

Show First 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
define void @add_64i(i64* %p) { define void @add_64i(i64* %p) {
; X64-LABEL: add_64i: ; X64-LABEL: add_64i:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: addq $2, (%rdi) ; X64-NEXT: addq $2, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_64i: ; X32-LABEL: add_64i:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $2, %ebx ; X32-NEXT: addl $2, %ebx
; X32-NEXT: adcl $0, %ecx ; X32-NEXT: adcl $0, %ecx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB14_1: # %atomicrmw.start ; X32-NEXT: .LBB14_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB14_1 ; X32-NEXT: jne .LBB14_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'addq'. ; We do not check X86-32 as it cannot do 'addq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = add i64 %1, 2 %2 = add i64 %1, 2
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
define void @add_64r(i64* %p, i64 %v) { define void @add_64r(i64* %p, i64 %v) {
; X64-LABEL: add_64r: ; X64-LABEL: add_64r:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: addq %rsi, (%rdi) ; X64-NEXT: addq %rsi, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_64r: ; X32-LABEL: add_64r:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: addl 12(%ebp), %ebx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: adcl 16(%ebp), %ecx
; X32-NEXT: addl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: adcl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB15_1: # %atomicrmw.start ; X32-NEXT: .LBB15_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB15_1 ; X32-NEXT: jne .LBB15_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'addq'. ; We do not check X86-32 as it cannot do 'addq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = add i64 %1, %v %2 = add i64 %1, %v
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
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define void @sub_64r(i64* %p, i64 %v) { define void @sub_64r(i64* %p, i64 %v) {
; X64-LABEL: sub_64r: ; X64-LABEL: sub_64r:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq %rsi, (%rdi) ; X64-NEXT: subq %rsi, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: sub_64r: ; X32-LABEL: sub_64r:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: subl 12(%ebp), %ebx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: sbbl 16(%ebp), %ecx
; X32-NEXT: subl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB23_1: # %atomicrmw.start ; X32-NEXT: .LBB23_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB23_1 ; X32-NEXT: jne .LBB23_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'subq'. ; We do not check X86-32 as it cannot do 'subq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = sub i64 %1, %v %2 = sub i64 %1, %v
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
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define void @and_64i(i64* %p) { define void @and_64i(i64* %p) {
; X64-LABEL: and_64i: ; X64-LABEL: and_64i:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andq $2, (%rdi) ; X64-NEXT: andq $2, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: and_64i: ; X32-LABEL: and_64i:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: andl $2, %ebx ; X32-NEXT: andl $2, %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: xorl %ecx, %ecx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB31_1: # %atomicrmw.start ; X32-NEXT: .LBB31_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB31_1 ; X32-NEXT: jne .LBB31_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'andq'. ; We do not check X86-32 as it cannot do 'andq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = and i64 %1, 2 %2 = and i64 %1, 2
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
define void @and_64r(i64* %p, i64 %v) { define void @and_64r(i64* %p, i64 %v) {
; X64-LABEL: and_64r: ; X64-LABEL: and_64r:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andq %rsi, (%rdi) ; X64-NEXT: andq %rsi, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: and_64r: ; X32-LABEL: and_64r:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: andl 16(%ebp), %ecx
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: andl 12(%ebp), %ebx
; X32-NEXT: andl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: andl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB32_1: # %atomicrmw.start ; X32-NEXT: .LBB32_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB32_1 ; X32-NEXT: jne .LBB32_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'andq'. ; We do not check X86-32 as it cannot do 'andq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = and i64 %1, %v %2 = and i64 %1, %v
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
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define void @or_64i(i64* %p) { define void @or_64i(i64* %p) {
; X64-LABEL: or_64i: ; X64-LABEL: or_64i:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orq $2, (%rdi) ; X64-NEXT: orq $2, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: or_64i: ; X32-LABEL: or_64i:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: orl $2, %ebx ; X32-NEXT: orl $2, %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB41_1: # %atomicrmw.start ; X32-NEXT: .LBB41_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB41_1 ; X32-NEXT: jne .LBB41_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'orq'. ; We do not check X86-32 as it cannot do 'orq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = or i64 %1, 2 %2 = or i64 %1, 2
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
define void @or_64r(i64* %p, i64 %v) { define void @or_64r(i64* %p, i64 %v) {
; X64-LABEL: or_64r: ; X64-LABEL: or_64r:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orq %rsi, (%rdi) ; X64-NEXT: orq %rsi, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: or_64r: ; X32-LABEL: or_64r:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: orl 16(%ebp), %ecx
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: orl 12(%ebp), %ebx
; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: orl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB42_1: # %atomicrmw.start ; X32-NEXT: .LBB42_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB42_1 ; X32-NEXT: jne .LBB42_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'orq'. ; We do not check X86-32 as it cannot do 'orq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = or i64 %1, %v %2 = or i64 %1, %v
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
define void @xor_64i(i64* %p) { define void @xor_64i(i64* %p) {
; X64-LABEL: xor_64i: ; X64-LABEL: xor_64i:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorq $2, (%rdi) ; X64-NEXT: xorq $2, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: xor_64i: ; X32-LABEL: xor_64i:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: xorl $2, %ebx ; X32-NEXT: xorl $2, %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB51_1: # %atomicrmw.start ; X32-NEXT: .LBB51_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB51_1 ; X32-NEXT: jne .LBB51_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'xorq'. ; We do not check X86-32 as it cannot do 'xorq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = xor i64 %1, 2 %2 = xor i64 %1, 2
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
define void @xor_64r(i64* %p, i64 %v) { define void @xor_64r(i64* %p, i64 %v) {
; X64-LABEL: xor_64r: ; X64-LABEL: xor_64r:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorq %rsi, (%rdi) ; X64-NEXT: xorq %rsi, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: xor_64r: ; X32-LABEL: xor_64r:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: xorl 16(%ebp), %ecx
; X32-NEXT: movl %edx, %ecx ; X32-NEXT: xorl 12(%ebp), %ebx
; X32-NEXT: xorl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: xorl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB52_1: # %atomicrmw.start ; X32-NEXT: .LBB52_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB52_1 ; X32-NEXT: jne .LBB52_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'xorq'. ; We do not check X86-32 as it cannot do 'xorq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = xor i64 %1, %v %2 = xor i64 %1, %v
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
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define void @inc_64(i64* %p) { define void @inc_64(i64* %p) {
; FAST_INC-LABEL: inc_64: ; FAST_INC-LABEL: inc_64:
; FAST_INC: # %bb.0: ; FAST_INC: # %bb.0:
; FAST_INC-NEXT: incq (%rdi) ; FAST_INC-NEXT: incq (%rdi)
; FAST_INC-NEXT: retq ; FAST_INC-NEXT: retq
; ;
; X32-LABEL: inc_64: ; X32-LABEL: inc_64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $1, %ebx ; X32-NEXT: addl $1, %ebx
; X32-NEXT: adcl $0, %ecx ; X32-NEXT: adcl $0, %ecx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB58_1: # %atomicrmw.start ; X32-NEXT: .LBB58_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB58_1 ; X32-NEXT: jne .LBB58_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; SLOW_INC-LABEL: inc_64: ; SLOW_INC-LABEL: inc_64:
; SLOW_INC: # %bb.0: ; SLOW_INC: # %bb.0:
; SLOW_INC-NEXT: addq $1, (%rdi) ; SLOW_INC-NEXT: addq $1, (%rdi)
; SLOW_INC-NEXT: retq ; SLOW_INC-NEXT: retq
; We do not check X86-32 as it cannot do 'incq'. ; We do not check X86-32 as it cannot do 'incq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
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define void @dec_64(i64* %p) { define void @dec_64(i64* %p) {
; FAST_INC-LABEL: dec_64: ; FAST_INC-LABEL: dec_64:
; FAST_INC: # %bb.0: ; FAST_INC: # %bb.0:
; FAST_INC-NEXT: decq (%rdi) ; FAST_INC-NEXT: decq (%rdi)
; FAST_INC-NEXT: retq ; FAST_INC-NEXT: retq
; ;
; X32-LABEL: dec_64: ; X32-LABEL: dec_64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: addl $-1, %ebx ; X32-NEXT: addl $-1, %ebx
; X32-NEXT: adcl $-1, %ecx ; X32-NEXT: adcl $-1, %ecx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB63_1: # %atomicrmw.start ; X32-NEXT: .LBB63_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB63_1 ; X32-NEXT: jne .LBB63_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; SLOW_INC-LABEL: dec_64: ; SLOW_INC-LABEL: dec_64:
; SLOW_INC: # %bb.0: ; SLOW_INC: # %bb.0:
; SLOW_INC-NEXT: addq $-1, (%rdi) ; SLOW_INC-NEXT: addq $-1, (%rdi)
; SLOW_INC-NEXT: retq ; SLOW_INC-NEXT: retq
; We do not check X86-32 as it cannot do 'decq'. ; We do not check X86-32 as it cannot do 'decq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
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define void @not_64(i64* %p) { define void @not_64(i64* %p) {
; X64-LABEL: not_64: ; X64-LABEL: not_64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: notq (%rdi) ; X64-NEXT: notq (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: not_64: ; X32-LABEL: not_64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: .cfi_offset %esi, -12 ; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: xorl %edx, %edx ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: movl (%esp), %ebx
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %eax, %ebx
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: notl %ecx ; X32-NEXT: notl %ecx
; X32-NEXT: notl %ebx ; X32-NEXT: notl %ebx
; X32-NEXT: movl (%esi), %eax ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: movl 4(%esi), %edx ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB68_1: # %atomicrmw.start ; X32-NEXT: .LBB68_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: lock cmpxchg8b (%esi) ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: jne .LBB68_1 ; X32-NEXT: jne .LBB68_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do not check X86-32 as it cannot do 'notq'. ; We do not check X86-32 as it cannot do 'notq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = xor i64 %1, -1 %2 = xor i64 %1, -1
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
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define void @neg_64(i64* %p) { define void @neg_64(i64* %p) {
; X64-LABEL: neg_64: ; X64-LABEL: neg_64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: negq (%rdi) ; X64-NEXT: negq (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: neg_64: ; X32-LABEL: neg_64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: pushl %edi ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: .cfi_def_cfa_offset 12 ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: .cfi_def_cfa_offset 16 ; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $8, %esp
; X32-NEXT: .cfi_offset %esi, -16 ; X32-NEXT: .cfi_offset %esi, -16
; X32-NEXT: .cfi_offset %edi, -12 ; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: .cfi_offset %ebx, -8 ; X32-NEXT: movl 8(%ebp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi ; X32-NEXT: fildll (%esi)
; X32-NEXT: xorl %esi, %esi ; X32-NEXT: fistpll (%esp)
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: xorl %ecx, %ecx ; X32-NEXT: xorl %ecx, %ecx
; X32-NEXT: xorl %ebx, %ebx ; X32-NEXT: xorl %ebx, %ebx
; X32-NEXT: lock cmpxchg8b (%edi) ; X32-NEXT: subl (%esp), %ebx
; X32-NEXT: movl %eax, %ebx ; X32-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: negl %ebx ; X32-NEXT: movl (%esi), %eax
; X32-NEXT: sbbl %edx, %esi ; X32-NEXT: movl 4(%esi), %edx
; X32-NEXT: movl (%edi), %eax
; X32-NEXT: movl 4(%edi), %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB73_1: # %atomicrmw.start ; X32-NEXT: .LBB73_1: # %atomicrmw.start
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl %esi, %ecx ; X32-NEXT: lock cmpxchg8b (%esi)
; X32-NEXT: lock cmpxchg8b (%edi)
; X32-NEXT: jne .LBB73_1 ; X32-NEXT: jne .LBB73_1
; X32-NEXT: # %bb.2: # %atomicrmw.end ; X32-NEXT: # %bb.2: # %atomicrmw.end
; X32-NEXT: leal -8(%ebp), %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: .cfi_def_cfa_offset 12
; X32-NEXT: popl %edi
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
; We do neg check X86-32 as it canneg do 'negq'. ; We do neg check X86-32 as it canneg do 'negq'.
%1 = load atomic i64, i64* %p acquire, align 8 %1 = load atomic i64, i64* %p acquire, align 8
%2 = sub i64 0, %1 %2 = sub i64 0, %1
store atomic i64 %2, i64* %p release, align 8 store atomic i64 %2, i64* %p release, align 8
ret void ret void
} }
Show All 21 Lines

llvm/trunk/test/CodeGen/X86/atomic-non-integer.ll

Show First 20 Lines • Show All 442 Lines • ▼ Show 20 Lines
; X86-AVX-NEXT: vmovlps %xmm0, (%esp) ; X86-AVX-NEXT: vmovlps %xmm0, (%esp)
; X86-AVX-NEXT: fldl (%esp) ; X86-AVX-NEXT: fldl (%esp)
; X86-AVX-NEXT: addl $12, %esp ; X86-AVX-NEXT: addl $12, %esp
; X86-AVX-NEXT: .cfi_def_cfa_offset 4 ; X86-AVX-NEXT: .cfi_def_cfa_offset 4
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-NOSSE-LABEL: load_double: ; X86-NOSSE-LABEL: load_double:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: subl $20, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: pushl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
; X86-NOSSE-NEXT: subl $12, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24 ; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24
; X86-NOSSE-NEXT: .cfi_offset %esi, -12 ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: .cfi_offset %ebx, -8 ; X86-NOSSE-NEXT: fildll (%eax)
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ebx, %ebx
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, (%esp) ; X86-NOSSE-NEXT: movl %eax, (%esp)
; X86-NOSSE-NEXT: fldl (%esp) ; X86-NOSSE-NEXT: fldl (%esp)
; X86-NOSSE-NEXT: addl $12, %esp ; X86-NOSSE-NEXT: addl $20, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
; X86-NOSSE-NEXT: popl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: popl %ebx
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4 ; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X64-SSE-LABEL: load_double: ; X64-SSE-LABEL: load_double:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movq (%rdi), %xmm0 ; X64-SSE-NEXT: movq (%rdi), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
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; X86-AVX-NEXT: vmovlps %xmm0, (%esp) ; X86-AVX-NEXT: vmovlps %xmm0, (%esp)
; X86-AVX-NEXT: fldl (%esp) ; X86-AVX-NEXT: fldl (%esp)
; X86-AVX-NEXT: addl $12, %esp ; X86-AVX-NEXT: addl $12, %esp
; X86-AVX-NEXT: .cfi_def_cfa_offset 4 ; X86-AVX-NEXT: .cfi_def_cfa_offset 4
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-NOSSE-LABEL: load_double_seq_cst: ; X86-NOSSE-LABEL: load_double_seq_cst:
; X86-NOSSE: # %bb.0: ; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebx ; X86-NOSSE-NEXT: subl $20, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: pushl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
; X86-NOSSE-NEXT: subl $12, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24 ; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24
; X86-NOSSE-NEXT: .cfi_offset %esi, -12 ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: .cfi_offset %ebx, -8 ; X86-NOSSE-NEXT: fildll (%eax)
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %eax, %eax ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOSSE-NEXT: xorl %edx, %edx ; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOSSE-NEXT: xorl %ecx, %ecx ; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: xorl %ebx, %ebx
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: movl %eax, (%esp) ; X86-NOSSE-NEXT: movl %eax, (%esp)
; X86-NOSSE-NEXT: fldl (%esp) ; X86-NOSSE-NEXT: fldl (%esp)
; X86-NOSSE-NEXT: addl $12, %esp ; X86-NOSSE-NEXT: addl $20, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
; X86-NOSSE-NEXT: popl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: popl %ebx
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4 ; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X64-SSE-LABEL: load_double_seq_cst: ; X64-SSE-LABEL: load_double_seq_cst:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movq (%rdi), %rax ; X64-SSE-NEXT: movq (%rdi), %rax
; X64-SSE-NEXT: movq %rax, %xmm0 ; X64-SSE-NEXT: movq %rax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
Show All 9 Lines

llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines.: ; preds = %entry
unreachable unreachable
k.end: ; preds = %entry k.end: ; preds = %entry
unreachable unreachable
} }
declare i32 @m() declare i32 @m()
attributes #0 = { "no-frame-pointer-elim-non-leaf" } attributes #0 = { noimplicitfloat "no-frame-pointer-elim-non-leaf" }