[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.

[craig.topper]

Summary

This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes.

Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.

[craig.topper]

lib/Target/X86/X86FixupLEAs.cpp

158 ↗

(On Diff #193314)

I'll pull this out of this patch and rebase later today.

[craig.topper]

Rebase as the X86FixupLEAs.cpp change was commited to trunk.

[andreadb]

LGTM

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

enum : uint64_t {
     MRMSrcMemOp4   = 35,
 
     /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
     /// byte to specify the operands and also encodes a condition code.
     ///
     MRMSrcMemCC    = 36,
 
     /// MRMXm - This form is used for instructions that use the Mod/RM byte
+    /// to specify a memory source, but doesn't use the middle field. And has
+    /// a condition code.
+    ///
+    MRMXmCC = 38,
+
+    /// MRMXm - This form is used for instructions that use the Mod/RM byte
     /// to specify a memory source, but doesn't use the middle field.
     ///
-    MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
+    MRMXm = 39,
 
     // Next, instructions that operate on a memory r/m operand...
     MRM0m = 40,  MRM1m = 41,  MRM2m = 42,  MRM3m = 43, // Format /0 /1 /2 /3
     MRM4m = 44,  MRM5m = 45,  MRM6m = 46,  MRM7m = 47, // Format /4 /5 /6 /7
 
     /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
     /// to specify a destination, which in this case is a register.
     ///
enum : uint64_t {
     ///
     MRMSrcRegOp4   = 51,
 
     /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
     /// byte to specify the operands and also encodes a condition code
     ///
     MRMSrcRegCC    = 52,
 
+    /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
+    /// to specify a register source, but doesn't use the middle field. And has
+    /// a condition code.
+    ///
+    MRMXrCC = 54,
+
     /// MRMXr - This form is used for instructions that use the Mod/RM byte
     /// to specify a register source, but doesn't use the middle field.
     ///
-    MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
+    MRMXr = 55,
 
     // Instructions that operate on a register r/m operand...
     MRM0r = 56,  MRM1r = 57,  MRM2r = 58,  MRM3r = 59, // Format /0 /1 /2 /3
     MRM4r = 60,  MRM5r = 61,  MRM6r = 62,  MRM7r = 63, // Format /4 /5 /6 /7
 
     /// MRM_XX - A mod/rm byte of exactly 0xXX.
     MRM_C0 = 64,  MRM_C1 = 65,  MRM_C2 = 66,  MRM_C3 = 67,
     MRM_C4 = 68,  MRM_C5 = 69,  MRM_C6 = 70,  MRM_C7 = 71,
case X86II::MRMSrcMemCC:
       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
       // mask register.
       return 1;
     case X86II::MRMDestReg:
     case X86II::MRMSrcReg:
     case X86II::MRMSrcReg4VOp3:
     case X86II::MRMSrcRegOp4:
     case X86II::MRMSrcRegCC:
+    case X86II::MRMXrCC:
     case X86II::MRMXr:
     case X86II::MRM0r: case X86II::MRM1r:
     case X86II::MRM2r: case X86II::MRM3r:
     case X86II::MRM4r: case X86II::MRM5r:
     case X86II::MRM6r: case X86II::MRM7r:
       return -1;
+    case X86II::MRMXmCC:
     case X86II::MRMXm:
     case X86II::MRM0m: case X86II::MRM1m:
     case X86II::MRM2m: case X86II::MRM3m:
     case X86II::MRM4m: case X86II::MRM5m:
     case X86II::MRM6m: case X86II::MRM7m:
       // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
       return 0 + HasVEX_4V + HasEVEX_K;
     case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

case X86II::MRMDestReg:
     REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
     break;
   case X86II::MRMDestMem:
     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
     CurOp += X86::AddrNumOperands;
     REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
     break;
-  case X86II::MRMXm:
+  case X86II::MRMXmCC: case X86II::MRMXm:
   case X86II::MRM0m: case X86II::MRM1m:
   case X86II::MRM2m: case X86II::MRM3m:
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X
     break;
-  case X86II::MRMXr:
+  case X86II::MRMXrCC: case X86II::MRMXr:
   case X86II::MRM0r: case X86II::MRM1r:
   case X86II::MRM2r: case X86II::MRM3r:
   case X86II::MRM4r: case X86II::MRM5r:
   case X86II::MRM6r: case X86II::MRM7r:
     REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
     break;
   }
   if (REX && UsesHighByteReg)
case X86II::MRMSrcMemCC: {
     unsigned CC = MI.getOperand(CurOp++).getImm();
     EmitByte(BaseOpcode + CC, CurByte, OS);
 
     emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(RegOp)),
                      TSFlags, Rex, CurByte, OS, Fixups, STI);
     break;
   }
 
+  case X86II::MRMXrCC: {
+    unsigned RegOp = CurOp++;
+
+    unsigned CC = MI.getOperand(CurOp++).getImm();
+    EmitByte(BaseOpcode + CC, CurByte, OS);
+    EmitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS);
+    break;
+  }
+
   case X86II::MRMXr:
   case X86II::MRM0r: case X86II::MRM1r:
   case X86II::MRM2r: case X86II::MRM3r:
   case X86II::MRM4r: case X86II::MRM5r:
   case X86II::MRM6r: case X86II::MRM7r:
     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
       ++CurOp;
     if (HasEVEX_K) // Skip writemask
       ++CurOp;
     EmitByte(BaseOpcode, CurByte, OS);
     EmitRegModRMByte(MI.getOperand(CurOp++),
                      (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
                      CurByte, OS);
     break;
 
+  case X86II::MRMXmCC: {
+    unsigned FirstMemOp = CurOp;
+    CurOp = FirstMemOp + X86::AddrNumOperands;
+
+    unsigned CC = MI.getOperand(CurOp++).getImm();
+    EmitByte(BaseOpcode + CC, CurByte, OS);
+
+    emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Rex, CurByte, OS, Fixups, STI);
+    break;
+  }
+
   case X86II::MRMXm:
   case X86II::MRM0m: case X86II::MRM1m:
   case X86II::MRM2m: case X86II::MRM3m:
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
       ++CurOp;
     if (HasEVEX_K) // Skip writemask

llvm/lib/Target/X86/X86FastISel.cpp

bool X86FastISel::X86SelectCmp(const Instruction *I) {
   if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
     const auto *RHSC = dyn_cast<ConstantFP>(RHS);
     if (RHSC && RHSC->isNullValue())
       RHS = LHS;
   }
 
   // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
   static const uint16_t SETFOpcTable[2][3] = {
-    { X86::SETEr,  X86::SETNPr, X86::AND8rr },
-    { X86::SETNEr, X86::SETPr,  X86::OR8rr  }
+    { X86::COND_E,  X86::COND_NP, X86::AND8rr },
+    { X86::COND_NE, X86::COND_P,  X86::OR8rr  }
   };
   const uint16_t *SETFOpc = nullptr;
   switch (Predicate) {
   default: break;
   case CmpInst::FCMP_OEQ: SETFOpc = &SETFOpcTable[0][0]; break;
   case CmpInst::FCMP_UNE: SETFOpc = &SETFOpcTable[1][0]; break;
   }
 
   ResultReg = createResultReg(&X86::GR8RegClass);
   if (SETFOpc) {
     if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc()))
       return false;
 
     unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
     unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[0]),
-            FlagReg1);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[1]),
-            FlagReg2);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+            FlagReg1).addImm(SETFOpc[0]);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+            FlagReg2).addImm(SETFOpc[1]);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[2]),
             ResultReg).addReg(FlagReg1).addReg(FlagReg2);
     updateValueMap(I, ResultReg);
     return true;
   }
 
   X86::CondCode CC;
   bool SwapArgs;
   std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
   assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
-  unsigned Opc = X86::getSETFromCond(CC);
 
   if (SwapArgs)
     std::swap(LHS, RHS);
 
   // Emit a compare of LHS/RHS.
   if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc()))
     return false;
 
-  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
+  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+          ResultReg).addImm(CC);
   updateValueMap(I, ResultReg);
   return true;
 }
 
 bool X86FastISel::X86SelectZExt(const Instruction *I) {
   EVT DstVT = TLI.getValueType(DL, I->getType());
   if (!TLI.isTypeLegal(DstVT))
     return false;
bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
   // same basic block (values defined in other basic blocks may not have
   // initialized registers).
   const auto *CI = dyn_cast<CmpInst>(Cond);
   if (CI && (CI->getParent() == I->getParent())) {
     CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
 
     // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
     static const uint16_t SETFOpcTable[2][3] = {
-      { X86::SETNPr, X86::SETEr , X86::TEST8rr },
-      { X86::SETPr,  X86::SETNEr, X86::OR8rr   }
+      { X86::COND_NP, X86::COND_E,  X86::TEST8rr },
+      { X86::COND_P,  X86::COND_NE, X86::OR8rr   }
     };
     const uint16_t *SETFOpc = nullptr;
     switch (Predicate) {
     default: break;
     case CmpInst::FCMP_OEQ:
       SETFOpc = &SETFOpcTable[0][0];
       Predicate = CmpInst::ICMP_NE;
       break;
if (CI && (CI->getParent() == I->getParent())) {
     EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType());
     // Emit a compare of the LHS and RHS, setting the flags.
     if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc()))
       return false;
 
     if (SETFOpc) {
       unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
       unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[0]),
-              FlagReg1);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[1]),
-              FlagReg2);
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+              FlagReg1).addImm(SETFOpc[0]);
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+              FlagReg2).addImm(SETFOpc[1]);
       auto const &II = TII.get(SETFOpc[2]);
       if (II.getNumDefs()) {
         unsigned TmpReg = createResultReg(&X86::GR8RegClass);
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg)
           .addReg(FlagReg2).addReg(FlagReg1);
       } else {
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
           .addReg(FlagReg2).addReg(FlagReg1);
case Intrinsic::umul_with_overflow: {
     const Value *LHS = II->getArgOperand(0);
     const Value *RHS = II->getArgOperand(1);
 
     // Canonicalize immediate to the RHS.
     if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
         isCommutativeIntrinsic(II))
       std::swap(LHS, RHS);
 
-    unsigned BaseOpc, CondOpc;
+    unsigned BaseOpc, CondCode;
     switch (II->getIntrinsicID()) {
     default: llvm_unreachable("Unexpected intrinsic!");
     case Intrinsic::sadd_with_overflow:
-      BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break;
+      BaseOpc = ISD::ADD; CondCode = X86::COND_O; break;
     case Intrinsic::uadd_with_overflow:
-      BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break;
+      BaseOpc = ISD::ADD; CondCode = X86::COND_B; break;
     case Intrinsic::ssub_with_overflow:
-      BaseOpc = ISD::SUB; CondOpc = X86::SETOr; break;
+      BaseOpc = ISD::SUB; CondCode = X86::COND_O; break;
     case Intrinsic::usub_with_overflow:
-      BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break;
+      BaseOpc = ISD::SUB; CondCode = X86::COND_B; break;
     case Intrinsic::smul_with_overflow:
-      BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break;
+      BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break;
     case Intrinsic::umul_with_overflow:
-      BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break;
+      BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break;
     }
 
     unsigned LHSReg = getRegForValue(LHS);
     if (LHSReg == 0)
       return false;
     bool LHSIsKill = hasTrivialKill(LHS);
 
     unsigned ResultReg = 0;
     // Check if we have an immediate version.
     if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
       static const uint16_t Opc[2][4] = {
         { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
         { X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r }
       };
 
       if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) &&
-          CondOpc == X86::SETOr) {
+          CondCode == X86::COND_O) {
         // We can use INC/DEC.
         ResultReg = createResultReg(TLI.getRegClassFor(VT));
         bool IsDec = BaseOpc == ISD::SUB;
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
                 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
           .addReg(LHSReg, getKillRegState(LHSIsKill));
       } else
         ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
case Intrinsic::umul_with_overflow: {
     }
 
     if (!ResultReg)
       return false;
 
     // Assign to a GPR since the overflow return value is lowered to a SETcc.
     unsigned ResultReg2 = createResultReg(&X86::GR8RegClass);
     assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
-            ResultReg2);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
+            ResultReg2).addImm(CondCode);
 
     updateValueMap(II, ResultReg, 2);
     return true;
   }
   case Intrinsic::x86_sse_cvttss2si:
   case Intrinsic::x86_sse_cvttss2si64:
   case Intrinsic::x86_sse2_cvttsd2si:
   case Intrinsic::x86_sse2_cvttsd2si64: {

llvm/lib/Target/X86/X86FixupSetCC.cpp

private:
   static char ID;
 };
 
 char X86FixupSetCCPass::ID = 0;
 }
 
 FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
 
-bool X86FixupSetCCPass::isSetCCr(unsigned Opcode) {
-  switch (Opcode) {
-  default:
-    return false;
-  case X86::SETOr:
-  case X86::SETNOr:
-  case X86::SETBr:
-  case X86::SETAEr:
-  case X86::SETEr:
-  case X86::SETNEr:
-  case X86::SETBEr:
-  case X86::SETAr:
-  case X86::SETSr:
-  case X86::SETNSr:
-  case X86::SETPr:
-  case X86::SETNPr:
-  case X86::SETLr:
-  case X86::SETGEr:
-  case X86::SETLEr:
-  case X86::SETGr:
-    return true;
-  }
-}
-
 // We expect the instruction *immediately* before the setcc to imp-def
 // EFLAGS (because of scheduling glue). To make this less brittle w.r.t
 // scheduling, look backwards until we hit the beginning of the
 // basic-block, or a small bound (to avoid quadratic behavior).
 MachineInstr *
 X86FixupSetCCPass::findFlagsImpDef(MachineBasicBlock *MBB,
                                    MachineBasicBlock::reverse_iterator MI) {
   // FIXME: Should this be instr_rend(), and MI be reverse_instr_iterator?
bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
 
   SmallVector<MachineInstr*, 4> ToErase;
 
   for (auto &MBB : MF) {
     for (auto &MI : MBB) {
       // Find a setcc that is used by a zext.
       // This doesn't have to be the only use, the transformation is safe
       // regardless.
-      if (!isSetCCr(MI.getOpcode()))
+      if (MI.getOpcode() != X86::SETCCr)
         continue;
 
       MachineInstr *ZExt = nullptr;
       for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
         if (Use.getOpcode() == X86::MOVZX32rr8)
           ZExt = &Use;
 
       if (!ZExt)

llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

do {
                    X86::getCondFromBranchOpc(JmpIt->getOpcode()) !=
                        X86::COND_INVALID);
           break;
         }
 
         // Otherwise we can just rewrite in-place.
         if (X86::getCondFromCMov(MI) != X86::COND_INVALID) {
           rewriteCMov(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
-        } else if (X86::getCondFromSETOpc(MI.getOpcode()) !=
-                   X86::COND_INVALID) {
+        } else if (X86::getCondFromSETCC(MI) != X86::COND_INVALID) {
           rewriteSetCC(*TestMBB, TestPos, TestLoc, MI, *FlagUse, CondRegs);
         } else if (MI.getOpcode() == TargetOpcode::COPY) {
           rewriteCopy(MI, *FlagUse, CopyDefI);
         } else {
           // We assume all other instructions that use flags also def them.
           assert(MI.findRegisterDefOperand(X86::EFLAGS) &&
                  "Expected a def of EFLAGS for this instruction!");
 

 /// can re-use them rather than adding duplicates.
 CondRegArray X86FlagsCopyLoweringPass::collectCondsInRegs(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator TestPos) {
   CondRegArray CondRegs = {};
 
   // Scan backwards across the range of instructions with live EFLAGS.
   for (MachineInstr &MI :
        llvm::reverse(llvm::make_range(MBB.begin(), TestPos))) {
-    X86::CondCode Cond = X86::getCondFromSETOpc(MI.getOpcode());
+    X86::CondCode Cond = X86::getCondFromSETCC(MI);
     if (Cond != X86::COND_INVALID && !MI.mayStore() && MI.getOperand(0).isReg() &&
         TRI->isVirtualRegister(MI.getOperand(0).getReg())) {
       assert(MI.getOperand(0).isDef() &&
              "A non-storing SETcc should always define a register!");
       CondRegs[Cond] = MI.getOperand(0).getReg();
     }
 
     // Stop scanning when we see the first definition of the EFLAGS as prior to
     // this we would potentially capture the wrong flag state.
     if (MI.findRegisterDefOperand(X86::EFLAGS))
       break;
   }
   return CondRegs;
 }
 
 unsigned X86FlagsCopyLoweringPass::promoteCondToReg(
     MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
     DebugLoc TestLoc, X86::CondCode Cond) {
   unsigned Reg = MRI->createVirtualRegister(PromoteRC);
   auto SetI = BuildMI(TestMBB, TestPos, TestLoc,
-                      TII->get(X86::getSETFromCond(Cond)), Reg);
+                      TII->get(X86::SETCCr), Reg).addImm(Cond);
   (void)SetI;
   LLVM_DEBUG(dbgs() << "    save cond: "; SetI->dump());
   ++NumSetCCsInserted;
   return Reg;
 }
 
 std::pair<unsigned, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
     MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,

 }
 
 void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &TestMBB,
                                             MachineBasicBlock::iterator TestPos,
                                             DebugLoc TestLoc,
                                             MachineInstr &SetCCI,
                                             MachineOperand &FlagUse,
                                             CondRegArray &CondRegs) {
-  X86::CondCode Cond = X86::getCondFromSETOpc(SetCCI.getOpcode());
+  X86::CondCode Cond = X86::getCondFromSETCC(SetCCI);
   // Note that we can't usefully rewrite this to the inverse without complex
   // analysis of the users of the setCC. Largely we rely on duplicates which
   // could have been avoided already being avoided here.
   unsigned &CondReg = CondRegs[Cond];
   if (!CondReg)
     CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
 
   // Rewriting a register def is trivial: we just replace the register and

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

return CR && CR->getSignedMin().sge(-1ull << Width) &&
          CR->getSignedMax().slt(1ull << Width);
 }
 
 static X86::CondCode getCondFromNode(SDNode *N) {
   assert(N->isMachineOpcode() && "Unexpected node");
   X86::CondCode CC = X86::COND_INVALID;
   if (CC == X86::COND_INVALID)
     CC = X86::getCondFromBranchOpc(N->getMachineOpcode());
-  if (CC == X86::COND_INVALID)
-    CC = X86::getCondFromSETOpc(N->getMachineOpcode());
   if (CC == X86::COND_INVALID) {
     unsigned Opc = N->getMachineOpcode();
-    if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr || Opc == X86::CMOV64rr)
+    if (Opc == X86::SETCCr)
+      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(0));
+    else if (Opc == X86::SETCCm)
+      CC = static_cast<X86::CondCode>(N->getConstantOperandVal(5));
+    else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
+             Opc == X86::CMOV64rr)
       CC = static_cast<X86::CondCode>(N->getConstantOperandVal(2));
     else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
              Opc == X86::CMOV64rm)
       CC = static_cast<X86::CondCode>(N->getConstantOperandVal(6));
   }
 
   return CC;
 }

llvm/lib/Target/X86/X86InstrCMovSetCC.td

let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
   def CMOV64rm
     :RI<0x40, MRMSrcMemCC, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2, ccode:$cond),
         "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
         [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
                                   imm:$cond, EFLAGS))]>, TB;
 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
 } // isCodeGenOnly = 1, ForceDisassemble = 1
 
-multiclass CMOV_Aliases<string Name, int CC> {
-  def : InstAlias<Name#"{w}\t{$src, $dst|$dst, $src}",
+// SetCC instructions.
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
+  def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
+                "set${cond}\t$dst",
+                [(set GR8:$dst, (X86setcc imm:$cond, EFLAGS))]>,
+                TB, Sched<[WriteSETCC]>;
+  def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
+                "set${cond}\t$dst",
+                [(store (X86setcc imm:$cond, EFLAGS), addr:$dst)]>,
+                TB, Sched<[WriteSETCCStore]>;
+} // Uses = [EFLAGS]
+
+multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
+  def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
                   (CMOV16rr GR16:$dst, GR16:$src, CC), 0>;
-  def : InstAlias<Name#"{w}\t{$src, $dst|$dst, $src}",
+  def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
                   (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>;
-  def : InstAlias<Name#"{l}\t{$src, $dst|$dst, $src}",
+  def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
                   (CMOV32rr GR32:$dst, GR32:$src, CC), 0>;
-  def : InstAlias<Name#"{l}\t{$src, $dst|$dst, $src}",
+  def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
                   (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>;
-  def : InstAlias<Name#"{q}\t{$src, $dst|$dst, $src}",
+  def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
                   (CMOV64rr GR64:$dst, GR64:$src, CC), 0>;
-  def : InstAlias<Name#"{q}\t{$src, $dst|$dst, $src}",
+  def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
                   (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>;
-}
 
-defm : CMOV_Aliases<"cmovo" ,  0>;
-defm : CMOV_Aliases<"cmovno",  1>;
-defm : CMOV_Aliases<"cmovb" ,  2>;
-defm : CMOV_Aliases<"cmovae",  3>;
-defm : CMOV_Aliases<"cmove" ,  4>;
-defm : CMOV_Aliases<"cmovne",  5>;
-defm : CMOV_Aliases<"cmovbe",  6>;
-defm : CMOV_Aliases<"cmova" ,  7>;
-defm : CMOV_Aliases<"cmovs" ,  8>;
-defm : CMOV_Aliases<"cmovns",  9>;
-defm : CMOV_Aliases<"cmovp" , 10>;
-defm : CMOV_Aliases<"cmovnp", 11>;
-defm : CMOV_Aliases<"cmovl" , 12>;
-defm : CMOV_Aliases<"cmovge", 13>;
-defm : CMOV_Aliases<"cmovle", 14>;
-defm : CMOV_Aliases<"cmovg" , 15>;
-
-
-// SetCC instructions.
-multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
-  let Uses = [EFLAGS] in {
-    def r    : I<opc, MRMXr,  (outs GR8:$dst), (ins),
-                     !strconcat(Mnemonic, "\t$dst"),
-                     [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>,
-                     TB, Sched<[WriteSETCC]>;
-    def m    : I<opc, MRMXm,  (outs), (ins i8mem:$dst),
-                     !strconcat(Mnemonic, "\t$dst"),
-                     [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>,
-                     TB, Sched<[WriteSETCCStore]>;
-  } // Uses = [EFLAGS]
+  def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
+  def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
 }
 
-defm SETO  : SETCC<0x90, "seto",  X86_COND_O>;   // is overflow bit set
-defm SETNO : SETCC<0x91, "setno", X86_COND_NO>;  // is overflow bit not set
-defm SETB  : SETCC<0x92, "setb",  X86_COND_B>;   // unsigned less than
-defm SETAE : SETCC<0x93, "setae", X86_COND_AE>;  // unsigned greater or equal
-defm SETE  : SETCC<0x94, "sete",  X86_COND_E>;   // equal to
-defm SETNE : SETCC<0x95, "setne", X86_COND_NE>;  // not equal to
-defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>;  // unsigned less than or equal
-defm SETA  : SETCC<0x97, "seta",  X86_COND_A>;   // unsigned greater than
-defm SETS  : SETCC<0x98, "sets",  X86_COND_S>;   // is signed bit set
-defm SETNS : SETCC<0x99, "setns", X86_COND_NS>;  // is not signed
-defm SETP  : SETCC<0x9A, "setp",  X86_COND_P>;   // is parity bit set
-defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>;  // is parity bit not set
-defm SETL  : SETCC<0x9C, "setl",  X86_COND_L>;   // signed less than
-defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>;  // signed greater or equal
-defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>;  // signed less than or equal
-defm SETG  : SETCC<0x9F, "setg",  X86_COND_G>;   // signed greater than
+defm : CMOV_SETCC_Aliases<"o" ,  0>;
+defm : CMOV_SETCC_Aliases<"no",  1>;
+defm : CMOV_SETCC_Aliases<"b" ,  2>;
+defm : CMOV_SETCC_Aliases<"ae",  3>;
+defm : CMOV_SETCC_Aliases<"e" ,  4>;
+defm : CMOV_SETCC_Aliases<"ne",  5>;
+defm : CMOV_SETCC_Aliases<"be",  6>;
+defm : CMOV_SETCC_Aliases<"a" ,  7>;
+defm : CMOV_SETCC_Aliases<"s" ,  8>;
+defm : CMOV_SETCC_Aliases<"ns",  9>;
+defm : CMOV_SETCC_Aliases<"p" , 10>;
+defm : CMOV_SETCC_Aliases<"np", 11>;
+defm : CMOV_SETCC_Aliases<"l" , 12>;
+defm : CMOV_SETCC_Aliases<"ge", 13>;
+defm : CMOV_SETCC_Aliases<"le", 14>;
+defm : CMOV_SETCC_Aliases<"g" , 15>;
 
 // SALC is an undocumented instruction. Information for this instruction can be found
 // here http://www.rcollins.org/secrets/opcodes/SALC.html
 // Set AL if carry. 
 let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
   def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>;
 }

llvm/lib/Target/X86/X86InstrCompiler.td

 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
           (SETB_C64r)>;
 
 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
 // will be eliminated and that the sbb can be extended up to a wider type.  When
 // this happens, it is great.  However, if we are left with an 8-bit sbb and an
 // and, we might as well just match it as a setb.
 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
-          (SETBr)>;
+          (SETCCr (i8 2))>;
 
 // Patterns to give priority when both inputs are zero so that we don't use
 // an immediate for the RHS.
 // TODO: Should we use a 32-bit sbb for 8/16 to push the extract_subreg out?
 def : Pat<(X86sbb_flag (i8 0), (i8 0), EFLAGS),
           (SBB8rr (EXTRACT_SUBREG (MOV32r0), sub_8bit),
                   (EXTRACT_SUBREG (MOV32r0), sub_8bit))>;
 def : Pat<(X86sbb_flag (i16 0), (i16 0), EFLAGS),

llvm/lib/Target/X86/X86InstrFoldTables.cpp

static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
   { X86::MUL8r,               X86::MUL8m,               TB_FOLDED_LOAD },
   { X86::PEXTRDrr,            X86::PEXTRDmr,            TB_FOLDED_STORE },
   { X86::PEXTRQrr,            X86::PEXTRQmr,            TB_FOLDED_STORE },
   { X86::PTWRITE64r,          X86::PTWRITE64m,          TB_FOLDED_LOAD },
   { X86::PTWRITEr,            X86::PTWRITEm,            TB_FOLDED_LOAD },
   { X86::PUSH16r,             X86::PUSH16rmm,           TB_FOLDED_LOAD },
   { X86::PUSH32r,             X86::PUSH32rmm,           TB_FOLDED_LOAD },
   { X86::PUSH64r,             X86::PUSH64rmm,           TB_FOLDED_LOAD },
-  { X86::SETAEr,              X86::SETAEm,              TB_FOLDED_STORE },
-  { X86::SETAr,               X86::SETAm,               TB_FOLDED_STORE },
-  { X86::SETBEr,              X86::SETBEm,              TB_FOLDED_STORE },
-  { X86::SETBr,               X86::SETBm,               TB_FOLDED_STORE },
-  { X86::SETEr,               X86::SETEm,               TB_FOLDED_STORE },
-  { X86::SETGEr,              X86::SETGEm,              TB_FOLDED_STORE },
-  { X86::SETGr,               X86::SETGm,               TB_FOLDED_STORE },
-  { X86::SETLEr,              X86::SETLEm,              TB_FOLDED_STORE },
-  { X86::SETLr,               X86::SETLm,               TB_FOLDED_STORE },
-  { X86::SETNEr,              X86::SETNEm,              TB_FOLDED_STORE },
-  { X86::SETNOr,              X86::SETNOm,              TB_FOLDED_STORE },
-  { X86::SETNPr,              X86::SETNPm,              TB_FOLDED_STORE },
-  { X86::SETNSr,              X86::SETNSm,              TB_FOLDED_STORE },
-  { X86::SETOr,               X86::SETOm,               TB_FOLDED_STORE },
-  { X86::SETPr,               X86::SETPm,               TB_FOLDED_STORE },
-  { X86::SETSr,               X86::SETSm,               TB_FOLDED_STORE },
+  { X86::SETCCr,              X86::SETCCm,              TB_FOLDED_STORE },
   { X86::TAILJMPr,            X86::TAILJMPm,            TB_FOLDED_LOAD },
   { X86::TAILJMPr64,          X86::TAILJMPm64,          TB_FOLDED_LOAD },
   { X86::TAILJMPr64_REX,      X86::TAILJMPm64_REX,      TB_FOLDED_LOAD },
   { X86::TCRETURNri,          X86::TCRETURNmi,          TB_FOLDED_LOAD | TB_NO_FORWARD },
   { X86::TCRETURNri64,        X86::TCRETURNmi64,        TB_FOLDED_LOAD | TB_NO_FORWARD },
   { X86::TEST16ri,            X86::TEST16mi,            TB_FOLDED_LOAD },
   { X86::TEST16rr,            X86::TEST16mr,            TB_FOLDED_LOAD },
   { X86::TEST32ri,            X86::TEST32mi,            TB_FOLDED_LOAD },

llvm/lib/Target/X86/X86InstrFormats.td

 def RawFrmDstSrc  : Format<6>;
 def RawFrmImm8    : Format<7>;
 def RawFrmImm16   : Format<8>;
 def MRMDestMem     : Format<32>;
 def MRMSrcMem      : Format<33>;
 def MRMSrcMem4VOp3 : Format<34>;
 def MRMSrcMemOp4   : Format<35>;
 def MRMSrcMemCC    : Format<36>;
+def MRMXmCC: Format<38>;
 def MRMXm  : Format<39>;
 def MRM0m  : Format<40>;  def MRM1m  : Format<41>;  def MRM2m  : Format<42>;
 def MRM3m  : Format<43>;  def MRM4m  : Format<44>;  def MRM5m  : Format<45>;
 def MRM6m  : Format<46>;  def MRM7m  : Format<47>;
 def MRMDestReg     : Format<48>;
 def MRMSrcReg      : Format<49>;
 def MRMSrcReg4VOp3 : Format<50>;
 def MRMSrcRegOp4   : Format<51>;
 def MRMSrcRegCC    : Format<52>;
+def MRMXrCC: Format<54>;
 def MRMXr  : Format<55>;
 def MRM0r  : Format<56>;  def MRM1r  : Format<57>;  def MRM2r  : Format<58>;
 def MRM3r  : Format<59>;  def MRM4r  : Format<60>;  def MRM5r  : Format<61>;
 def MRM6r  : Format<62>;  def MRM7r  : Format<63>;
 def MRM_C0 : Format<64>;  def MRM_C1 : Format<65>;  def MRM_C2 : Format<66>;
 def MRM_C3 : Format<67>;  def MRM_C4 : Format<68>;  def MRM_C5 : Format<69>;
 def MRM_C6 : Format<70>;  def MRM_C7 : Format<71>;  def MRM_C8 : Format<72>;
 def MRM_C9 : Format<73>;  def MRM_CA : Format<74>;  def MRM_CB : Format<75>;

llvm/lib/Target/X86/X86InstrInfo.h

 
 // Turn condition code into conditional branch opcode.
 unsigned GetCondBranchFromCond(CondCode CC);
 
 /// Return a pair of condition code for the given predicate and whether
 /// the instruction operands should be swaped to match the condition code.
 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
 
-/// Return a set opcode for the given condition and whether it has
-/// a memory operand.
-unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
+/// Return a setcc opcode based on whether it has a memory operand.
+unsigned getSETOpc(bool HasMemoryOperand = false);
 
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
 
 // Turn jCC opcode into condition code.
 CondCode getCondFromBranchOpc(unsigned Opc);
 
 // Turn setCC opcode into condition code.
-CondCode getCondFromSETOpc(unsigned Opc);
+CondCode getCondFromSETCC(const MachineInstr &MI);
 
 // Turn CMov opcode into condition code.
 CondCode getCondFromCMov(const MachineInstr &MI);
 
 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
 /// e.g. turning COND_E to COND_NE.
 CondCode GetOppositeBranchCondition(CondCode CC);
 

llvm/lib/Target/X86/X86InstrInfo.cpp

X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
   case X86::JNS_1: return X86::COND_NS;
   case X86::JP_1:  return X86::COND_P;
   case X86::JNP_1: return X86::COND_NP;
   case X86::JO_1:  return X86::COND_O;
   case X86::JNO_1: return X86::COND_NO;
   }
 }
 
-/// Return condition code of a SET opcode.
-X86::CondCode X86::getCondFromSETOpc(unsigned Opc) {
-  switch (Opc) {
+/// Return condition code of a SETCC opcode.
+X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
-  case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
-  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
-  case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
-  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
-  case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
-  case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
-  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
-  case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
-  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
-  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
-  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
-  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
-  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
-  case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
-  case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
-  case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
+  case X86::SETCCr: case X86::SETCCm:
+    return static_cast<X86::CondCode>(
+        MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
   }
 }
 
 /// Return condition code of a CMov opcode.
 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return X86::COND_INVALID;
   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
   }
 
   return std::make_pair(CC, NeedSwap);
 }
 
-/// Return a set opcode for the given condition and
-/// whether it has memory operand.
-unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
-  static const uint16_t Opc[16][2] = {
-    { X86::SETOr,  X86::SETOm  },
-    { X86::SETNOr, X86::SETNOm },
-    { X86::SETBr,  X86::SETBm  },
-    { X86::SETAEr, X86::SETAEm },
-    { X86::SETEr,  X86::SETEm  },
-    { X86::SETNEr, X86::SETNEm },
-    { X86::SETBEr, X86::SETBEm },
-    { X86::SETAr,  X86::SETAm  },
-    { X86::SETSr,  X86::SETSm  },
-    { X86::SETNSr, X86::SETNSm },
-    { X86::SETPr,  X86::SETPm  },
-    { X86::SETNPr, X86::SETNPm },
-    { X86::SETLr,  X86::SETLm  },
-    { X86::SETGEr, X86::SETGEm },
-    { X86::SETLEr, X86::SETLEm },
-    { X86::SETGr,  X86::SETGm  },
-  };
-
-  assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
-  return Opc[CC][HasMemoryOperand ? 1 : 0];
+/// Return a setcc opcode based on whether it has memory operand.
+unsigned X86::getSETOpc(bool HasMemoryOperand) {
+  return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
 }
 
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
   switch(RegBytes) {
   default: llvm_unreachable("Illegal register size!");
   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
                     Sub->getOperand(2).getReg() == SrcReg);
 
   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
   // If we are done with the basic block, we need to check whether EFLAGS is
   // live-out.
   bool IsSafe = false;
-  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
+  SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
   for (++I; I != E; ++I) {
     const MachineInstr &Instr = *I;
     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
     // We should check the usage if this instruction uses and updates EFLAGS.
     if (!UseEFLAGS && ModifyEFLAGS) {
       // It is safe to remove CmpInstr if EFLAGS is updated again.
       IsSafe = true;
       break;
     }
     if (!UseEFLAGS && !ModifyEFLAGS)
       continue;
 
     // EFLAGS is used by this instruction.
     X86::CondCode OldCC = X86::COND_INVALID;
-    bool OpcIsSET = false;
     if (IsCmpZero || IsSwapped) {
       // We decode the condition code from opcode.
       if (Instr.isBranch())
         OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
       else {
-        OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
-        if (OldCC != X86::COND_INVALID)
-          OpcIsSET = true;
-        else
+        OldCC = X86::getCondFromSETCC(Instr);
+        if (OldCC == X86::COND_INVALID)
           OldCC = X86::getCondFromCMov(Instr);
       }
       if (OldCC == X86::COND_INVALID) return false;
     }
     X86::CondCode ReplacementCC = X86::COND_INVALID;
     if (IsCmpZero) {
       switch (OldCC) {
       default: break;
if (IsCmpZero) {
       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
       // We swap the condition code and synthesize the new opcode.
       ReplacementCC = getSwappedCondition(OldCC);
       if (ReplacementCC == X86::COND_INVALID) return false;
     }
 
     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
-      // Synthesize the new opcode.
-      bool HasMemoryOperand = Instr.hasOneMemOperand();
-      unsigned NewOpc;
-      if (Instr.isBranch())
-        NewOpc = GetCondBranchFromCond(ReplacementCC);
-      else if(OpcIsSET)
-        NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
-      else {
-        NewOpc = ReplacementCC;
-      }
-
       // Push the MachineInstr to OpsToUpdate.
       // If it is safe to remove CmpInstr, the condition code of these
       // instructions will be modified.
-      OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
+      OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
     }
     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
       IsSafe = true;
       break;
     }
   }
 
for (; i != e; ++i) {
     }
   }
   assert(i != e && "Unable to locate a def EFLAGS operand");
 
   CmpInstr.eraseFromParent();
 
   // Modify the condition code of instructions in OpsToUpdate.
   for (auto &Op : OpsToUpdate) {
-    if (X86::getCondFromCMov(*Op.first) != X86::COND_INVALID)
+    if (Op.first->isBranch())
+      Op.first->setDesc(get(GetCondBranchFromCond(Op.second)));
+    else
       Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
           .setImm(Op.second);
-    else
-      Op.first->setDesc(get(Op.second));
   }
   return true;
 }
 
 /// Try to remove the load by folding it to a register
 /// operand at the use. We fold the load instructions if load defines a virtual
 /// register, the virtual register is used once in the same BB, and the
 /// instructions in-between do not load or store, and have no side effects.

llvm/lib/Target/X86/X86InstructionSelector.cpp

bool X86InstructionSelector::selectCmp(MachineInstr &I,
                                        MachineRegisterInfo &MRI,
                                        MachineFunction &MF) const {
   assert((I.getOpcode() == TargetOpcode::G_ICMP) && "unexpected instruction");
 
   X86::CondCode CC;
   bool SwapArgs;
   std::tie(CC, SwapArgs) = X86::getX86ConditionCode(
       (CmpInst::Predicate)I.getOperand(1).getPredicate());
-  unsigned OpSet = X86::getSETFromCond(CC);
 
   unsigned LHS = I.getOperand(2).getReg();
   unsigned RHS = I.getOperand(3).getReg();
 
   if (SwapArgs)
     std::swap(LHS, RHS);
 
   unsigned OpCmp;
bool X86InstructionSelector::selectCmp(MachineInstr &I,
   }
 
   MachineInstr &CmpInst =
       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
            .addReg(LHS)
            .addReg(RHS);
 
   MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                                   TII.get(OpSet), I.getOperand(0).getReg());
+                                   TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
 
   constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
   constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
 
   I.eraseFromParent();
   return true;
 }
 
 bool X86InstructionSelector::selectFCmp(MachineInstr &I,
                                         MachineRegisterInfo &MRI,
                                         MachineFunction &MF) const {
   assert((I.getOpcode() == TargetOpcode::G_FCMP) && "unexpected instruction");
 
   unsigned LhsReg = I.getOperand(2).getReg();
   unsigned RhsReg = I.getOperand(3).getReg();
   CmpInst::Predicate Predicate =
       (CmpInst::Predicate)I.getOperand(1).getPredicate();
 
   // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
   static const uint16_t SETFOpcTable[2][3] = {
-      {X86::SETEr, X86::SETNPr, X86::AND8rr},
-      {X86::SETNEr, X86::SETPr, X86::OR8rr}};
+      {X86::COND_E, X86::COND_NP, X86::AND8rr},
+      {X86::COND_NE, X86::COND_P, X86::OR8rr}};
   const uint16_t *SETFOpc = nullptr;
   switch (Predicate) {
   default:
     break;
   case CmpInst::FCMP_OEQ:
     SETFOpc = &SETFOpcTable[0][0];
     break;
   case CmpInst::FCMP_UNE:
if (SETFOpc) {
     MachineInstr &CmpInst =
         *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
              .addReg(LhsReg)
              .addReg(RhsReg);
 
     unsigned FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
     unsigned FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
     MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                                  TII.get(SETFOpc[0]), FlagReg1);
+                                  TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
     MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                                  TII.get(SETFOpc[1]), FlagReg2);
+                                  TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
     MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
                                   TII.get(SETFOpc[2]), ResultReg)
                               .addReg(FlagReg1)
                               .addReg(FlagReg2);
     constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
     constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
     constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
     constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
 
     I.eraseFromParent();
     return true;
   }
 
   X86::CondCode CC;
   bool SwapArgs;
   std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
   assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
-  unsigned Opc = X86::getSETFromCond(CC);
 
   if (SwapArgs)
     std::swap(LhsReg, RhsReg);
 
   // Emit a compare of LHS/RHS.
   MachineInstr &CmpInst =
       *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
            .addReg(LhsReg)
            .addReg(RhsReg);
 
   MachineInstr &Set =
-      *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc), ResultReg);
+      *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
   constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
   constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
   I.eraseFromParent();
   return true;
 }
 
 bool X86InstructionSelector::selectUadde(MachineInstr &I,
                                          MachineRegisterInfo &MRI,

llvm/lib/Target/X86/X86SchedBroadwell.td

def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let ResourceCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup20], (instrs CWD,
                                          JCXZ, JECXZ, JRCXZ,
                                          ADC8i8, SBB8i8,
                                          ADC16i16, SBB16i16,
                                          ADC32i32, SBB32i32,
                                          ADC64i32, SBB64i32)>;
-def: InstRW<[BWWriteResGroup20], (instregex "SET(A|BE)r")>;
 
 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
   let Latency = 2;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 

 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 
 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
-def: InstRW<[BWWriteResGroup38], (instregex "SET(A|BE)m")>;
 
 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
   let Latency = 4;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
                                             "(V?)CVT(T?)SD2SIrr",

 def BWCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
+// SETCCs that use both Z and C flag require an extra uop.
+def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
+  let Latency = 2;
+  let ResourceCycles = [1,1];
+  let NumMicroOps = 2;
+}
+
+def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
+  let Latency = 3;
+  let ResourceCycles = [1,1,1,1];
+  let NumMicroOps = 4;
+}
+
+def BWSETA_SETBErr :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
+  SchedVar<NoSchedPred,                         [WriteSETCC]>
+]>;
+
+def BWSETA_SETBErm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>,
+  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
+]>;
+
+def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>;
+def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>;
+
 } // SchedModel

llvm/lib/Target/X86/X86SchedHaswell.td

 def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
 
 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
-def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>;
 
 def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 7;
   let NumMicroOps = 3;
   let ResourceCycles = [2,1];
 }
 def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm,
                                            MMX_PACKSSWBirm,

 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
 
 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
-def: InstRW<[HWWriteResGroup45], (instregex "SET(A|BE)m")>;
 
 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
   let Latency = 8;
   let NumMicroOps = 5;
   let ResourceCycles = [1,1,1,2];
 }
 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
                                             "ROR(8|16|32|64)m(1|i)")>;

 def HWCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
+// SETCCs that use both Z and C flag require an extra uop.
+def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
+  let Latency = 2;
+  let ResourceCycles = [1,1];
+  let NumMicroOps = 2;
+}
+
+def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
+  let Latency = 3;
+  let ResourceCycles = [1,1,1,1];
+  let NumMicroOps = 4;
+}
+
+def HWSETA_SETBErr :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,
+  SchedVar<NoSchedPred,                         [WriteSETCC]>
+]>;
+
+def HWSETA_SETBErm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>,
+  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
+]>;
+
+def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>;
+def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>;
+
 } // SchedModel

llvm/lib/Target/X86/X86SchedPredicates.td

def IsCMOVArr_Or_CMOVBErr : CheckAny<[
   CheckImmOperand_s<3, "X86::COND_A">,
   CheckImmOperand_s<3, "X86::COND_BE">
 ]>;
 
 def IsCMOVArm_Or_CMOVBErm : CheckAny<[
   CheckImmOperand_s<7, "X86::COND_A">,
   CheckImmOperand_s<7, "X86::COND_BE">
 ]>;
+
+// A predicate to check for COND_A and COND_BE SETCCs which have an extra uop
+// on recent Intel CPUs.
+def IsSETAr_Or_SETBEr : CheckAny<[
+  CheckImmOperand_s<1, "X86::COND_A">,
+  CheckImmOperand_s<1, "X86::COND_BE">
+]>;
+
+def IsSETAm_Or_SETBEm : CheckAny<[
+  CheckImmOperand_s<5, "X86::COND_A">,
+  CheckImmOperand_s<5, "X86::COND_BE">
+]>;

llvm/lib/Target/X86/X86SchedSandyBridge.td

def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
                                         MMX_PABSDrr,
                                         MMX_PABSWrr,
                                         MMX_PADDQirr,
                                         MMX_PALIGNRrri,
                                         MMX_PSIGNBrr,
                                         MMX_PSIGNDrr,
                                         MMX_PSIGNWrr)>;
 
-def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [2];
-}
-def: InstRW<[SBWriteResGroup9], (instregex "SET(A|BE)r")>;
-
 def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SBWriteResGroup11], (instrs SCASB,
                                          SCASL,
                                          SCASQ,

 
 def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
   let Latency = 5;
   let NumMicroOps = 4;
   let ResourceCycles = [1,3];
 }
 def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
 
-def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
-  let Latency = 3;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
-}
-def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>;
-
 def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
   let Latency = 5;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
 def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
                                             "PUSHF(16|64)")>;
 

 def SBCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
+// SETCCs that use both Z and C flag require an extra uop.
+def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> {
+  let Latency = 2;
+  let ResourceCycles = [2];
+  let NumMicroOps = 2;
+}
+
+def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
+  let Latency = 3;
+  let ResourceCycles = [1,1,2];
+  let NumMicroOps = 4;
+}
+
+def SBSETA_SETBErr :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>,
+  SchedVar<NoSchedPred,                         [WriteSETCC]>
+]>;
+
+def SBSETA_SETBErm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>,
+  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
+]>;
+
+def : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>;
+def : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>;
+
 } // SchedModel

llvm/lib/Target/X86/X86SchedSkylakeClient.td

 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
                                           MMX_MOVDQ2Qrr)>;
 
-def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [2];
-}
-def: InstRW<[SKLWriteResGroup15], (instregex "SET(A|BE)r")>;
-
 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
                                           WAIT,
                                           XGETBV)>;

 
 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
   let Latency = 3;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 
-def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
-  let Latency = 3;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
-}
-def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
-
 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 
 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {

 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
+// SETCCs that use both Z and C flag require an extra uop.
+def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
+  let Latency = 2;
+  let ResourceCycles = [2];
+  let NumMicroOps = 2;
+}
+
+def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
+  let Latency = 3;
+  let ResourceCycles = [1,1,2];
+  let NumMicroOps = 4;
+}
+
+def SKLSETA_SETBErr :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
+  SchedVar<NoSchedPred,                         [WriteSETCC]>
+]>;
+
+def SKLSETA_SETBErm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
+  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
+]>;
+
+def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
+def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
+
 } // SchedModel

llvm/lib/Target/X86/X86SchedSkylakeServer.td

 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
                                           MMX_MOVDQ2Qrr)>;
 
-def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [2];
-}
-def: InstRW<[SKXWriteResGroup15], (instregex "SET(A|BE)r")>;
-
 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
                                           WAIT,
                                           XGETBV)>;

 
 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
   let Latency = 3;
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 
-def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
-  let Latency = 3;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1,1,2];
-}
-def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>;
-
 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
   let Latency = 3;
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 
 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {

 def SKXCMOVA_CMOVBErm :  SchedWriteVariant<[
   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
 ]>;
 
 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
 
+// SETCCs that use both Z and C flag require an extra uop.
+def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
+  let Latency = 2;
+  let ResourceCycles = [2];
+  let NumMicroOps = 2;
+}
+
+def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
+  let Latency = 3;
+  let ResourceCycles = [1,1,2];
+  let NumMicroOps = 4;
+}
+
+def SKXSETA_SETBErr :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
+  SchedVar<NoSchedPred,                         [WriteSETCC]>
+]>;
+
+def SKXSETA_SETBErm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
+  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
+]>;
+
+def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
+def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
+
 } // SchedModel

llvm/lib/Target/X86/X86ScheduleBdVer2.td

 
 def : WriteRes<WriteSETCC,           [PdEX01]>; // Setcc.
 def : WriteRes<WriteSETCCStore,      [PdEX01, PdStore]>;
 
 def PdWriteSETGEmSETGmSETLEmSETLm : SchedWriteRes<[PdEX01]> {
   let ResourceCycles = [2];
   let NumMicroOps = 2;
 }
-def : InstRW<[PdWriteSETGEmSETGmSETLEmSETLm], (instrs SETGEm, SETGm,
-                                                      SETLEm, SETLm)>;
+
+def PdSETGEmSETGmSETLEmSETLm :  SchedWriteVariant<[
+  SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_GE">>, [PdWriteSETGEmSETGmSETLEmSETLm]>,
+  SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_G">>,  [PdWriteSETGEmSETGmSETLEmSETLm]>,
+  SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_LE">>, [PdWriteSETGEmSETGmSETLEmSETLm]>,
+  SchedVar<MCSchedPredicate<CheckImmOperand_s<5, "X86::COND_L">>,  [PdWriteSETGEmSETGmSETLEmSETLm]>,
+  SchedVar<NoSchedPred,                                            [WriteSETCCStore]>
+]>;
+def : InstRW<[PdSETGEmSETGmSETLEmSETLm], (instrs SETCCm)>;
 
 defm : PdWriteRes<WriteLAHFSAHF,      [PdEX01],          2,  [],     2>;
 
 def WriteLAHF : SchedWriteRes<[PdEX01]> {
   let Latency = 2;
   let NumMicroOps = 4;
 }
 def : InstRW<[WriteLAHF], (instrs LAHF)>;

llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i8
     ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil
     ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
     ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s8) = COPY $dil
     %1(s8) = COPY $sil
     %2(s1) = G_ICMP intpred(eq), %0(s8), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i16
     ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di
     ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
     ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s16) = COPY $di
     %1(s16) = COPY $si
     %2(s1) = G_ICMP intpred(eq), %0(s16), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: test_icmp_eq_i64
     ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
     ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %2(s1) = G_ICMP intpred(eq), %0(s64), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(eq), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ne_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(ne), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ugt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_uge_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(uge), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ult_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(ult), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ule_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(ule), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sgt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sge_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETGEr:%[0-9]+]]:gr8 = SETGEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(sge), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_slt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETLr:%[0-9]+]]:gr8 = SETLr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(slt), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)

 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sle_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETLEr:%[0-9]+]]:gr8 = SETLEr implicit $eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], %subreg.sub_8bit
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
     ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(sle), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-phi.mir

body:             |
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
   ; ALL:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.2, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   $al = COPY [[PHI]]
   ; ALL:   RET 0, implicit $al
   bb.1.entry:
body:             |
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
   ; ALL:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.2, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   $ax = COPY [[PHI]]
   ; ALL:   RET 0, implicit $ax
   bb.1.entry:
body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr32 = COPY $edx
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.1, implicit $eflags
   ; ALL:   JMP_1 %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   JMP_1 %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $rdx, $rsi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
   ; ALL:   [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.1, implicit $eflags
   ; ALL:   JMP_1 %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   JMP_1 %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
body:             |
   ; ALL:   liveins: $edi, $xmm0, $xmm1
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL:   [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
   ; ALL:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL:   [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.2, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
   ; ALL:   $xmm0 = COPY [[COPY5]]
   ; ALL:   RET 0, implicit $xmm0
body:             |
   ; ALL:   liveins: $edi, $xmm0, $xmm1
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL:   [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
   ; ALL:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL:   [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
   ; ALL:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
   ; ALL:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
-  ; ALL:   [[SETGr:%[0-9]+]]:gr8 = SETGr implicit $eflags
-  ; ALL:   TEST8ri [[SETGr]], 1, implicit-def $eflags
+  ; ALL:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+  ; ALL:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL:   JNE_1 %bb.2, implicit $eflags
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
   ; ALL:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
   ; ALL:   $xmm0 = COPY [[COPY5]]
   ; ALL:   RET 0, implicit $xmm0

llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir

bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_oeq
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SETNPr:%[0-9]+]]:gr8 = SETNPr implicit $eflags
-    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETEr]], [[SETNPr]], implicit-def $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
     ; CHECK: $al = COPY [[AND8rr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(oeq), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ogt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags
-    ; CHECK: $al = COPY [[SETAr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ogt), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_oge
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags
-    ; CHECK: $al = COPY [[SETAEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(oge), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_olt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags
-    ; CHECK: $al = COPY [[SETAr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(olt), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ole
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags
-    ; CHECK: $al = COPY [[SETAEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ole), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_one
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags
-    ; CHECK: $al = COPY [[SETNEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(one), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ord
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNPr:%[0-9]+]]:gr8 = SETNPr implicit $eflags
-    ; CHECK: $al = COPY [[SETNPr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ord), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_uno
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETPr:%[0-9]+]]:gr8 = SETPr implicit $eflags
-    ; CHECK: $al = COPY [[SETPr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(uno), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ueq
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: $al = COPY [[SETEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ueq), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ugt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ugt), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_uge
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags
-    ; CHECK: $al = COPY [[SETBEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(uge), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ult
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ult), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_ule
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags
-    ; CHECK: $al = COPY [[SETBEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ule), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_float_une
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
     ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags
-    ; CHECK: [[SETPr:%[0-9]+]]:gr8 = SETPr implicit $eflags
-    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETNEr]], [[SETPr]], implicit-def $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
     ; CHECK: $al = COPY [[OR8rr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s32) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s32) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(une), %0(s32), %1
     %5:gpr(s8) = COPY %6(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_oeq
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: [[SETNPr:%[0-9]+]]:gr8 = SETNPr implicit $eflags
-    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETEr]], [[SETNPr]], implicit-def $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+    ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
     ; CHECK: $al = COPY [[AND8rr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(oeq), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ogt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags
-    ; CHECK: $al = COPY [[SETAr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ogt), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_oge
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags
-    ; CHECK: $al = COPY [[SETAEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(oge), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_olt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit $eflags
-    ; CHECK: $al = COPY [[SETAr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(olt), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ole
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit $eflags
-    ; CHECK: $al = COPY [[SETAEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ole), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_one
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags
-    ; CHECK: $al = COPY [[SETNEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(one), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ord
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNPr:%[0-9]+]]:gr8 = SETNPr implicit $eflags
-    ; CHECK: $al = COPY [[SETNPr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ord), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_uno
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETPr:%[0-9]+]]:gr8 = SETPr implicit $eflags
-    ; CHECK: $al = COPY [[SETPr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(uno), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ueq
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit $eflags
-    ; CHECK: $al = COPY [[SETEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ueq), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ugt
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ugt), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_uge
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags
-    ; CHECK: $al = COPY [[SETBEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(uge), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ult
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit $eflags
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ult), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_ule
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit $eflags
-    ; CHECK: $al = COPY [[SETBEr]]
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(ule), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: fcmp_double_une
     ; CHECK: liveins: $xmm0, $xmm1
     ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
     ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
     ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
     ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
     ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
-    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit $eflags
-    ; CHECK: [[SETPr:%[0-9]+]]:gr8 = SETPr implicit $eflags
-    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETNEr]], [[SETPr]], implicit-def $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+    ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
     ; CHECK: $al = COPY [[OR8rr]]
     ; CHECK: RET 0, implicit $al
     %2:vecr(s128) = COPY $xmm0
     %0:vecr(s64) = G_TRUNC %2(s128)
     %3:vecr(s128) = COPY $xmm1
     %1:vecr(s64) = G_TRUNC %3(s128)
     %6:gpr(s8) = G_FCMP floatpred(une), %0(s64), %1
     %5:gpr(s8) = COPY %6(s8)
     $al = COPY %5(s8)
     RET 0, implicit $al
 
 ...

llvm/test/CodeGen/X86/flags-copy-lowering.mir

bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     JA_1 %bb.1, implicit $eflags
bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     JA_1 %bb.2, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
-  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
-  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETNEr implicit $eflags
+  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
+  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETCCr 5, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
-    %3:gr8 = SETAr implicit $eflags
-    %4:gr8 = SETBr implicit $eflags
-    %5:gr8 = SETEr implicit $eflags
-    SETNEm $rsp, 1, $noreg, -16, $noreg, implicit killed $eflags
+    %3:gr8 = SETCCr 7, implicit $eflags
+    %4:gr8 = SETCCr 2, implicit $eflags
+    %5:gr8 = SETCCr 4, implicit $eflags
+    SETCCm $rsp, 1, $noreg, -16, $noreg, 5, implicit killed $eflags
     MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %3
     MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %4
     MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %5
   ; CHECK-NOT:     $eflags =
   ; CHECK-NOT:             = SET{{.*}}
   ; CHECK:         MOV8mr {{.*}}, killed %[[A_REG]]
   ; CHECK-NEXT:    MOV8mr {{.*}}, killed %[[B_REG]]
   ; CHECK-NEXT:    MOV8mr {{.*}}, killed %[[E_REG]]
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
-  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
+  ; CHECK:      %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
+  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     %3:gr64 = CMOV64rr %0, %1, 7, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = ADC64ri32 %2:gr64, 42, implicit-def $eflags, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = SUB64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY killed $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = SBB64ri32 %2:gr64, 42, implicit-def $eflags, implicit killed $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
-  ; CHECK:        %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
-  ; CHECK-NEXT:   %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:        %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = CMOV64rr %0, %1, 4, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
-  ; CHECK:        %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
-  ; CHECK-NEXT:   %[[OF_REG:[^:]*]]:gr8 = SETOr implicit $eflags
+  ; CHECK:        %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   %[[OF_REG:[^:]*]]:gr8 = SETCCr 0, implicit $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = CMOV64rr %0, %1, 4, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = RCL64r1 %2:gr64, implicit-def $eflags, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
   
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr64 = RCR64r1 %2:gr64, implicit-def $eflags, implicit $eflags
body:             |
   bb.0:
     liveins: $rdi, $rsi
 
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     %2:gr64 = ADD64rr %0, %1, implicit-def $eflags
     %3:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[CF_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %3
     %4:gr8 = SETB_C8r implicit-def $eflags, implicit $eflags
bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
 
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[S_REG:[^:]*]]:gr8 = SETSr implicit $eflags
-  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETNEr implicit $eflags
-  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:      %[[S_REG:[^:]*]]:gr8 = SETCCr 8, implicit $eflags
+  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETCCr 5, implicit $eflags
+  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     JA_1 %bb.1, implicit $eflags
bb.0:
     successors: %bb.1, %bb.2, %bb.5
     liveins: $rdi, $rsi
 
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
     %2:gr64 = COPY $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
-  ; CHECK:      %[[S_REG:[^:]*]]:gr8 = SETSr implicit $eflags
-  ; CHECK-NEXT: %[[P_REG:[^:]*]]:gr8 = SETPr implicit $eflags
-  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETNEr implicit $eflags
-  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
-  ; CHECK-NEXT: %[[O_REG:[^:]*]]:gr8 = SETOr implicit $eflags
+  ; CHECK:      %[[S_REG:[^:]*]]:gr8 = SETCCr 8, implicit $eflags
+  ; CHECK-NEXT: %[[P_REG:[^:]*]]:gr8 = SETCCr 10, implicit $eflags
+  ; CHECK-NEXT: %[[NE_REG:[^:]*]]:gr8 = SETCCr 5, implicit $eflags
+  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
+  ; CHECK-NEXT: %[[O_REG:[^:]*]]:gr8 = SETCCr 0, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     JA_1 %bb.1, implicit $eflags
bb.1:
     successors: %bb.2, %bb.4
     liveins: $eflags
 
     ; Outer loop header, target for one set of hoisting.
     JE_1 %bb.2, implicit $eflags
     JMP_1 %bb.4
   ; CHECK:      bb.1:
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
-  ; CHECK:        %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT:   %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
-  ; CHECK-NEXT:   %[[B_REG:[^:]*]]:gr8 = SETBr implicit $eflags
+  ; CHECK:        %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT:   %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
+  ; CHECK-NEXT:   %[[B_REG:[^:]*]]:gr8 = SETCCr 2, implicit $eflags
   ; CHECK-NOT:    COPY{{( killed)?}} $eflags
 
   bb.2:
     successors: %bb.2, %bb.3
     liveins: $eflags
 
     ; Inner loop with a local copy. We should eliminate this but can't hoist.
     %2:gr64 = COPY $eflags

 body:             |
   bb.0:
     successors: %bb.1, %bb.2, %bb.3
     liveins: $rdi, $rsi
 
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
-    %2:gr8 = SETAr implicit $eflags
-    %3:gr8 = SETAEr implicit $eflags
+    %2:gr8 = SETCCr 7, implicit $eflags
+    %3:gr8 = SETCCr 3, implicit $eflags
     %4:gr64 = COPY $eflags
   ; CHECK:      CMP64rr %0, %1, implicit-def $eflags
-  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags
-  ; CHECK-NEXT: %[[AE_REG:[^:]*]]:gr8 = SETAEr implicit $eflags
+  ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETCCr 7, implicit $eflags
+  ; CHECK-NEXT: %[[AE_REG:[^:]*]]:gr8 = SETCCr 3, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %4
     JA_1 %bb.1, implicit $eflags

 body:             |
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $rdi, $rsi
 
     %0:gr64 = COPY $rdi
     %1:gr64 = COPY $rsi
     CMP64rr %0, %1, implicit-def $eflags
-    SETEm %0, 1, $noreg, -16, $noreg, implicit $eflags
+    SETCCm %0, 1, $noreg, -16, $noreg, 4, implicit $eflags
     %2:gr64 = COPY $eflags
   ; CHECK:      CMP64rr %0, %1, implicit-def $eflags
   ; We cannot reuse this SETE because it stores the flag directly to memory,
   ; so we have two SETEs here. FIXME: It'd be great if something could fold
   ; these automatically. If not, maybe we want to unfold SETcc instructions
   ; writing to memory so we can reuse them.
-  ; CHECK-NEXT: SETEm {{.*}} implicit $eflags
-  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags
+  ; CHECK-NEXT: SETCCm {{.*}} 4, implicit $eflags
+  ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETCCr 4, implicit $eflags
   ; CHECK-NOT:  COPY{{( killed)?}} $eflags
 
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
     CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
 
     $eflags = COPY %2
     JE_1 %bb.1, implicit $eflags

llvm/test/CodeGen/X86/pr27681.mir

bb.0:
     $edx = MOV32ri 6
 
   bb.1:
     liveins: $eax, $ebp, $ebx, $ecx, $edi, $edx
 
     $ebp = SHR32rCL killed $ebp, implicit-def dead $eflags, implicit $cl
     $ebp = XOR32rr killed $ebp, killed $ebx, implicit-def dead $eflags
     TEST32rr $edx, $edx, implicit-def $eflags
-    $cl = SETNEr implicit $eflags
+    $cl = SETCCr 5, implicit $eflags
     ; This %bl def is antidependent on the above use of $ebx
     $bl = MOV8rm $esp, 1, $noreg, 3, _ ; :: (load 1 from %stack.0)
     $cl = OR8rr killed $cl, $bl, implicit-def dead $eflags
     $esi = MOVZX32rr8 killed $cl
     $esi = ADD32rr killed $esi, killed $edi, implicit-def dead $eflags
     $ecx = MOV32rm $esp, 1, $noreg, 24, _ ; :: (load 4 from %stack.2)
     $edx = SAR32rCL killed $edx, implicit-def dead $eflags, implicit $cl
     TEST32rr killed $edx, $edx, implicit-def $eflags
-    $cl = SETNEr implicit $eflags
+    $cl = SETCCr 5, implicit $eflags
     ; Verify that removal of the $bl antidependence does not use $ch
     ; as a replacement register.
     ; CHECK: $cl = AND8rr killed $cl, killed $b
     $cl = AND8rr killed $cl, killed $bl, implicit-def dead $eflags
     CMP32ri8 $ebp, -1, implicit-def $eflags
     $edx = MOV32ri 0
     JE_1 %bb.3, implicit $eflags
 
   bb.2:
     liveins: $cl, $eax, $ebp, $esi
 
     OR32mr $esp, 1, $noreg, 8, $noreg, killed $eax, implicit-def $eflags ; :: (store 4 into %stack.1)
-    $dl = SETNEr implicit $eflags, implicit-def $edx
+    $dl = SETCCr 5, implicit $eflags, implicit-def $edx
 
   bb.3:
     liveins: $cl, $ebp, $edx, $esi
 
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
     $esp = ADD32ri8 $esp, 36, implicit-def dead $eflags
     $esi = POP32r implicit-def $esp, implicit $esp
     $edi = POP32r implicit-def $esp, implicit $esp
     $ebx = POP32r implicit-def $esp, implicit $esp
     $ebp = POP32r implicit-def $esp, implicit $esp
     RET 0, $eax
 
 ...

llvm/test/CodeGen/X86/stack-folding-adx.mir

bb.0 (%ir-block.0):
     ; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
     ; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
     ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
     ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
     ; CHECK: [[ADCX32rm:%[0-9]+]]:gr32 = ADCX32rm [[ADCX32rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 4 from %stack.1)
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit killed $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV32mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADCX32rm]] :: (store 4 into %ir.4, align 1)
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, $al
     %3:gr64 = COPY $rcx
     %2:gr32 = COPY $edx
     %7:gr32 = COPY $esi
     %0:gr32 = COPY $edi
     INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     dead %0.sub_8bit:gr32 = ADD8ri %0.sub_8bit, -1, implicit-def $eflags
     %7:gr32 = ADCX32rr %7, %2, implicit-def $eflags, implicit killed $eflags
-    %8:gr8 = SETBr implicit killed $eflags
+    %8:gr8 = SETCCr 2, implicit killed $eflags
     MOV32mr %3, 1, $noreg, 0, $noreg, %7 :: (store 4 into %ir.4, align 1)
     $al = COPY %8
     RET 0, killed $al
 
 ...
 ---
 name:            stack_fold_adcx64
 alignment:       4
bb.0 (%ir-block.0):
     ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
     ; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
     ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
     ; CHECK: [[ADCX64rm:%[0-9]+]]:gr64 = ADCX64rm [[ADCX64rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 8 from %stack.1)
-    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit killed $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV64mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADCX64rm]] :: (store 8 into %ir.4, align 1)
-    ; CHECK: $al = COPY [[SETBr]]
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, $al
     %3:gr64 = COPY $rcx
     %2:gr64 = COPY $rdx
     %7:gr64 = COPY $rsi
     %0:gr32 = COPY $edi
     INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     dead %0.sub_8bit:gr32 = ADD8ri %0.sub_8bit, -1, implicit-def $eflags
     %7:gr64 = ADCX64rr %7, %2, implicit-def $eflags, implicit killed $eflags
-    %8:gr8 = SETBr implicit killed $eflags
+    %8:gr8 = SETCCr 2, implicit killed $eflags
     MOV64mr %3, 1, $noreg, 0, $noreg, %7 :: (store 8 into %ir.4, align 1)
     $al = COPY %8
     RET 0, killed $al
 
 ...
 ---
 name:            stack_fold_adox32
 alignment:       4
bb.0 (%ir-block.0):
     ; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
     ; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
     ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
     ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
     ; CHECK: [[ADOX32rm:%[0-9]+]]:gr32 = ADOX32rm [[ADOX32rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 4 from %stack.1)
-    ; CHECK: [[SETOr:%[0-9]+]]:gr8 = SETOr implicit killed $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 0, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV32mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADOX32rm]] :: (store 4 into %ir.4, align 1)
-    ; CHECK: $al = COPY [[SETOr]]
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, $al
     %3:gr64 = COPY $rcx
     %2:gr32 = COPY $edx
     %7:gr32 = COPY $esi
     %0:gr32 = COPY $edi
     INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     dead %0.sub_8bit:gr32 = ADD8ri %0.sub_8bit, 127, implicit-def $eflags
     %7:gr32 = ADOX32rr %7, %2, implicit-def $eflags, implicit killed $eflags
-    %8:gr8 = SETOr implicit killed $eflags
+    %8:gr8 = SETCCr 0, implicit killed $eflags
     MOV32mr %3, 1, $noreg, 0, $noreg, %7 :: (store 4 into %ir.4, align 1)
     $al = COPY %8
     RET 0, killed $al
 
 ...
 ---
 name:            stack_fold_adox64
 alignment:       4
bb.0 (%ir-block.0):
     ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
     ; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
     ; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
     ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
     ; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
     ; CHECK: [[ADOX64rm:%[0-9]+]]:gr64 = ADOX64rm [[ADOX64rm]], %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit killed $eflags :: (load 8 from %stack.1)
-    ; CHECK: [[SETOr:%[0-9]+]]:gr8 = SETOr implicit killed $eflags
+    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 0, implicit killed $eflags
     ; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
     ; CHECK: MOV64mr [[MOV64rm]], 1, $noreg, 0, $noreg, [[ADOX64rm]] :: (store 8 into %ir.4, align 1)
-    ; CHECK: $al = COPY [[SETOr]]
+    ; CHECK: $al = COPY [[SETCCr]]
     ; CHECK: RET 0, $al
     %3:gr64 = COPY $rcx
     %2:gr64 = COPY $rdx
     %7:gr64 = COPY $rsi
     %0:gr32 = COPY $edi
     INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
     dead %0.sub_8bit:gr32 = ADD8ri %0.sub_8bit, 127, implicit-def $eflags
     %7:gr64 = ADOX64rr %7, %2, implicit-def $eflags, implicit killed $eflags
-    %8:gr8 = SETOr implicit killed $eflags
+    %8:gr8 = SETCCr 0, implicit killed $eflags
     MOV64mr %3, 1, $noreg, 0, $noreg, %7 :: (store 8 into %ir.4, align 1)
     $al = COPY %8
     RET 0, killed $al
 
 ...

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

static Error isInvalidMemoryInstr(const Instruction &Instr) {
   // These have no memory access.
   case X86II::Pseudo:
   case X86II::RawFrm:
   case X86II::MRMDestReg:
   case X86II::MRMSrcReg:
   case X86II::MRMSrcReg4VOp3:
   case X86II::MRMSrcRegOp4:
   case X86II::MRMSrcRegCC:
+  case X86II::MRMXrCC:
   case X86II::MRMXr:
   case X86II::MRM0r:
   case X86II::MRM1r:
   case X86II::MRM2r:
   case X86II::MRM3r:
   case X86II::MRM4r:
   case X86II::MRM5r:
   case X86II::MRM6r:
return (Instr.Description->Opcode == X86::POP16r || Instr.Description->Opcode == X86::POP32r ||
                      "unsupported opcode: unsupported memory access")
                : Error::success();
   // These access memory and are handled.
   case X86II::MRMDestMem:
   case X86II::MRMSrcMem:
   case X86II::MRMSrcMem4VOp3:
   case X86II::MRMSrcMemOp4:
   case X86II::MRMSrcMemCC:
+  case X86II::MRMXmCC:
   case X86II::MRMXm:
   case X86II::MRM0m:
   case X86II::MRM1m:
   case X86II::MRM2m:
   case X86II::MRM3m:
   case X86II::MRM4m:
   case X86II::MRM5m:
   case X86II::MRM6m:

llvm/utils/TableGen/X86RecognizableInstr.h

enum {
     RawFrmDstSrc  = 6,
     RawFrmImm8    = 7,
     RawFrmImm16   = 8,
     MRMDestMem     = 32,
     MRMSrcMem      = 33,
     MRMSrcMem4VOp3 = 34,
     MRMSrcMemOp4   = 35,
     MRMSrcMemCC    = 36,
-    MRMXm = 39,
+    MRMXmCC = 38, MRMXm = 39,
     MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
     MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,
     MRMDestReg     = 48,
     MRMSrcReg      = 49,
     MRMSrcReg4VOp3 = 50,
     MRMSrcRegOp4   = 51,
     MRMSrcRegCC    = 52,
-    MRMXr = 55,
+    MRMXrCC = 54, MRMXr = 55,
     MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59,
     MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63,
 #define MAP(from, to) MRM_##from = to,
     X86_INSTR_MRM_MAPPING
 #undef MAP
   };
 
   enum {

llvm/utils/TableGen/X86RecognizableInstr.cpp

case X86Local::MRMSrcMemOp4:
     break;
   case X86Local::MRMSrcMemCC:
     assert(numPhysicalOperands == 3 &&
            "Unexpected number of operands for MRMSrcMemCC");
     HANDLE_OPERAND(roRegister)
     HANDLE_OPERAND(memory)
     HANDLE_OPERAND(opcodeModifier)
     break;
+  case X86Local::MRMXrCC:
+    assert(numPhysicalOperands == 2 &&
+           "Unexpected number of operands for MRMXrCC");
+    HANDLE_OPERAND(rmRegister)
+    HANDLE_OPERAND(opcodeModifier)
+    break;
   case X86Local::MRMXr:
   case X86Local::MRM0r:
   case X86Local::MRM1r:
   case X86Local::MRM2r:
   case X86Local::MRM3r:
   case X86Local::MRM4r:
   case X86Local::MRM5r:
   case X86Local::MRM6r:
if (HasVEX_4V)
       HANDLE_OPERAND(vvvvRegister)
 
     if (HasEVEX_K)
       HANDLE_OPERAND(writemaskRegister)
     HANDLE_OPTIONAL(rmRegister)
     HANDLE_OPTIONAL(relocation)
     HANDLE_OPTIONAL(immediate)
     break;
+  case X86Local::MRMXmCC:
+    assert(numPhysicalOperands == 2 &&
+           "Unexpected number of operands for MRMXm");
+    HANDLE_OPERAND(memory)
+    HANDLE_OPERAND(opcodeModifier)
+    break;
   case X86Local::MRMXm:
   case X86Local::MRM0m:
   case X86Local::MRM1m:
   case X86Local::MRM2m:
   case X86Local::MRM3m:
   case X86Local::MRM4m:
   case X86Local::MRM5m:
   case X86Local::MRM6m:
#define MAP(from, to)                     \
   case X86Local::RawFrmImm16:
     filter = llvm::make_unique<DumbFilter>();
     break;
   case X86Local::MRMDestReg:
   case X86Local::MRMSrcReg:
   case X86Local::MRMSrcReg4VOp3:
   case X86Local::MRMSrcRegOp4:
   case X86Local::MRMSrcRegCC:
+  case X86Local::MRMXrCC:
   case X86Local::MRMXr:
     filter = llvm::make_unique<ModFilter>(true);
     break;
   case X86Local::MRMDestMem:
   case X86Local::MRMSrcMem:
   case X86Local::MRMSrcMem4VOp3:
   case X86Local::MRMSrcMemOp4:
   case X86Local::MRMSrcMemCC:
+  case X86Local::MRMXmCC:
   case X86Local::MRMXm:
     filter = llvm::make_unique<ModFilter>(false);
     break;
   case X86Local::MRM0r: case X86Local::MRM1r:
   case X86Local::MRM2r: case X86Local::MRM3r:
   case X86Local::MRM4r: case X86Local::MRM5r:
   case X86Local::MRM6r: case X86Local::MRM7r:
     filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
#define MAP(from, to)                     \
   case X86Local::AdSize32: AddressSize = 32; break;
   case X86Local::AdSize64: AddressSize = 64; break;
   }
 
   assert(opcodeType && "Opcode type not set");
   assert(filter && "Filter not set");
 
   if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
-      Form == X86Local::MRMSrcMemCC) {
+      Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
+      Form == X86Local::MRMXmCC) {
     unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
     assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
 
     uint8_t currentOpcode;
 
     for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count;
          ++currentOpcode)
       tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,