[mips] Remove unused FGRH32 register class. NFC

[atanasyan]

Summary

If we need this class in the future we will easily restore it.

[Petar.Avramovic]

LGTM.

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

private:
   /// Coerce the register to FGR32 and return the real register for the current
   /// target.
   unsigned getFGR32Reg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
     return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
         .getRegister(RegIdx.Index);
   }
 
-  /// Coerce the register to FGRH32 and return the real register for the current
-  /// target.
-  unsigned getFGRH32Reg() const {
-    assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
-    return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
-        .getRegister(RegIdx.Index);
-  }
-
   /// Coerce the register to FCC and return the real register for the current
   /// target.
   unsigned getFCCReg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
     return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
         .getRegister(RegIdx.Index);
   }
 
void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
     // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
     if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
       AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
                                 "registers");
   }
 
-  void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
-    assert(N == 1 && "Invalid number of operands!");
-    Inst.addOperand(MCOperand::createReg(getFGRH32Reg()));
-  }
-
   void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFCCReg()));
   }
 
   void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getMSA128Reg()));

llvm/lib/Target/Mips/MipsRegisterInfo.td

def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> {
   // Do not allocate odd registers when given -mattr=+nooddspreg.
   let AltOrders = [(decimate FGR32, 2)];
   let AltOrderSelect = [{
     const auto & S = MF.getSubtarget<MipsSubtarget>();
     return S.isABI_O32() && !S.useOddSPReg();
   }];
 }
 
-def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
-             Unallocatable {
-  // Do not allocate odd registers when given -mattr=+nooddspreg.
-  let AltOrders = [(decimate FGRH32, 2)];
-  let AltOrderSelect = [{
-    const auto & S = MF.getSubtarget<MipsSubtarget>();
-    return S.isABI_O32() && !S.useOddSPReg();
-  }];
-}
-
 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
   // Return Values and Arguments
   D0, D1,
   // Not preserved across procedure calls
   D2, D3, D4, D5,
   // Return Values and Arguments
   D6, D7,
   // Not preserved across procedure calls
def FGR32AsmOperand : MipsAsmRegOperand {
   let PredicateMethod = "isFGRAsmReg";
 }
 
 def StrictlyFGR32AsmOperand : MipsAsmRegOperand {
   let Name = "StrictlyFGR32AsmReg";
   let PredicateMethod = "isStrictlyFGRAsmReg";
 }
 
-def FGRH32AsmOperand : MipsAsmRegOperand {
-  let Name = "FGRH32AsmReg";
-  let PredicateMethod = "isFGRAsmReg";
-}
-
 def FCCRegsAsmOperand : MipsAsmRegOperand {
   let Name = "FCCAsmReg";
 }
 
 def MSA128AsmOperand : MipsAsmRegOperand {
   let Name = "MSA128AsmReg";
 }
 

 }
 
 def FGRCCOpnd : RegisterOperand<FGRCC> {
   // The assembler doesn't use register classes so we can re-use
   // FGR32AsmOperand.
   let ParserMatchClass = FGR32AsmOperand;
 }
 
-def FGRH32Opnd : RegisterOperand<FGRH32> {
-  let ParserMatchClass = FGRH32AsmOperand;
-}
-
 def FCCRegsOpnd : RegisterOperand<FCC> {
   let ParserMatchClass = FCCRegsAsmOperand;
 }
 
 def LO32DSPOpnd : RegisterOperand<LO32DSP> {
   let ParserMatchClass = LO32DSPAsmOperand;
 }