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[InstCombine] eliminate commuted select-shuffles + binop (PR41304)
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Authored by spatel on Mar 31 2019, 9:50 AM.

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Summary

If we have a commutable vector binop with inverted select-shuffles, we don't care about the order of the operands in each vector lane:

LHS = shuffle V1, V2, <0, 5, 6, 3>
RHS = shuffle V2, V1, <0, 5, 6, 3>
LHS + RHS --> (V10+V20, V21+V11, V22+V12, V13+V23) --> V1 + V2

PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...is titled as an SLP enhancement, but at least for the given example, we can reduce that in instcombine because we are just eliminating shuffles.
As noted in the TODO, this could be generalized, but I haven't thought through those patterns completely, so this is limited to what appears to be always safe.

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rL LLVM

Event Timeline

spatel created this revision.Mar 31 2019, 9:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 31 2019, 9:50 AM
xbolva00 added inline comments.
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
1429 ↗(On Diff #193018)

typo?

lebedev.ri accepted this revision.Mar 31 2019, 11:19 AM

This LG, thanks.

This revision is now accepted and ready to land.Mar 31 2019, 11:19 AM
spatel marked 2 inline comments as done.Apr 1 2019, 6:13 AM
spatel added inline comments.
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
1429 ↗(On Diff #193018)

Yep - fixed.

This revision was automatically updated to reflect the committed changes.
spatel marked an inline comment as done.