AMDGPU: Ignore SRAM ECC feature when inlining

[rampitec]

LGTM

[arsenm]

This isn't correct, this does impact codegen. This changes whether d16 instruction can be used

[arsenm]

Non ECC functions can safely call ECC functions, but not the other way around. Can you add tests for both directions?

[rampitec]

In D59717#1440117, @arsenm wrote:

This isn't correct, this does impact codegen. This changes whether d16 instruction can be used

But these instructions created after any inlining.

[arsenm]

In D59717#1440169, @rampitec wrote:

In D59717#1440117, @arsenm wrote:

This isn't correct, this does impact codegen. This changes whether d16 instruction can be used

But these instructions created after any inlining.

The features should be consistent with no knowledge of the function body. An ecc function calling a non-ecc function is potentially broken, so it shouldn’t be inlined

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

const FeatureBitset InlineFeatureIgnoreList = {
 
     AMDGPU::FeatureAutoWaitcntBeforeBarrier,
 
     // Property of the kernel/environment which can't actually differ.
     AMDGPU::FeatureSGPRInitBug,
     AMDGPU::FeatureXNACK,
     AMDGPU::FeatureTrapHandler,
     AMDGPU::FeatureCodeObjectV3,
+    AMDGPU::FeatureSRAMECC,
 
     // Perf-tuning features
     AMDGPU::FeatureFastFMAF32,
     AMDGPU::HalfRate64Ops
   };
 
   const GCNSubtarget *getST() const { return ST; }
   const AMDGPUTargetLowering *getTLI() const { return TLI; }

test/Transforms/Inline/AMDGPU/inline-target-cpu.ll

 
 ; CHECK-LABEL: @disable_codeobjectv3_call_codeobjectv3(
 ; CHECK-NEXT: ret i32 999
 define i32 @disable_codeobjectv3_call_codeobjectv3() #11 {
   %call = call i32 @enable_codeobjectv3()
   ret i32 %call
 }
 
+define i32 @sram_ecc_on() #12 {
+  ret i32 1
+}
+
+; CHECK-LABEL: @sram_ecc_off_calls_sram_ecc_on(
+; CHECK-NEXT: ret i32 1
+define i32 @sram_ecc_off_calls_sram_ecc_on() #13 {
+  %call = call i32 @sram_ecc_on()
+  ret i32 %call
+}
+
 attributes #0 = { nounwind }
 attributes #1 = { nounwind "target-cpu"="fiji" }
 attributes #2 = { nounwind "target-cpu"="fiji" "target-features"="+fp32-denormals" }
 attributes #3 = { nounwind "target-features"="+fp32-denormals" }
 attributes #4 = { nounwind "target-features"="-fp32-denormals" }
 attributes #5 = { nounwind "target-cpu"="gfx900" }
 attributes #6 = { nounwind "target-features"="-half-rate-64-ops" }
 attributes #7 = { nounwind "target-features"="+half-rate-64-ops" }
 attributes #8 = { nounwind "target-features"="-load-store-opt" }
 attributes #9 = { nounwind "target-features"="+load-store-opt" }
 attributes #10 = { nounwind "target-features"="+code-object-v3" }
 attributes #11 = { nounwind "target-features"="-code-object-v3" }
+attributes #12 = { nounwind "target-features"="+sram-ecc" }
+attributes #13 = { nounwind "target-features"="-sram-ecc" }