[ARM] Optimize expressions like "return x != 0;" for Thumb1.

[efriedma]

Summary

There's an existing optimization for x != C, but somehow it was missing a special case for 0.

While I'm here, also cleaned up the code/comments a bit: the second value produced by the MERGE_VALUES was actually dead, since a CMOV only produces one result.

[dmgreen]

Looks like a nice improvement to me.

Can you add some extra testing where the shift is involved?

[efriedma]

Added a couple more tests, including one that generates the subs+sbcs+lsls sequence.

[dmgreen]

LGTM. Thanks.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

if (CC == ARMCC::EQ && !isNullConstant(RHS) &&
                         N->getOperand(3), CPSRGlue.getValue(1));
       FalseVal = Sub;
     }
   }
 
   // On Thumb1, the DAG above may be further combined if z is a power of 2
   // (z == 2 ^ K).
   // CMOV (SUBS x, y), z, !=, (SUBS x, y):1 ->
-  //       merge t3, t4
-  // where t1 = (SUBCARRY (SUB x, y), z, 0)
-  //       t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
-  //       t3 = if K != 0 then (SHL t2:0, K) else t2:0
-  //       t4 = (SUB 1, t2:1)   [ we want a carry, not a borrow ]
+  // t1 = (USUBO (SUB x, y), 1)
+  // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
+  // Result = if K != 0 then (SHL t2:0, K) else t2:0
+  //
+  // This also handles the special case of comparing against zero; it's
+  // essentially, the same pattern, except there's no SUBS:
+  // CMOV x, z, !=, (CMPZ x, 0) ->
+  // t1 = (USUBO x, 1)
+  // t2 = (SUBCARRY x, t1:0, t1:1)
+  // Result = if K != 0 then (SHL t2:0, K) else t2:0
   const APInt *TrueConst;
   if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&
-      (FalseVal.getOpcode() == ARMISD::SUBS) &&
-      (FalseVal.getOperand(0) == LHS) && (FalseVal.getOperand(1) == RHS) &&
+      ((FalseVal.getOpcode() == ARMISD::SUBS &&
+        FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) ||
+       (FalseVal == LHS && isNullConstant(RHS))) &&
       (TrueConst = isPowerOf2Constant(TrueVal))) {
     SDVTList VTs = DAG.getVTList(VT, MVT::i32);
     unsigned ShiftAmount = TrueConst->logBase2();
     if (ShiftAmount)
       TrueVal = DAG.getConstant(1, dl, VT);
     SDValue Subc = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, TrueVal);
     Res = DAG.getNode(ISD::SUBCARRY, dl, VTs, FalseVal, Subc, Subc.getValue(1));
-    // Make it a carry, not a borrow.
-    SDValue Carry = DAG.getNode(
-        ISD::SUB, dl, VT, DAG.getConstant(1, dl, MVT::i32), Res.getValue(1));
-    Res = DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Res, Carry);
 
     if (ShiftAmount)
       Res = DAG.getNode(ISD::SHL, dl, VT, Res,
                         DAG.getConstant(ShiftAmount, dl, MVT::i32));
   }
 
   if (Res.getNode()) {
     KnownBits Known = DAG.computeKnownBits(SDValue(N,0));

llvm/trunk/test/CodeGen/ARM/select-imm.ll

 define i32 @t6(i32 %a) nounwind {
 entry:
 ; ARM-LABEL: t6:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #0
 ; ARM: movne r0, #1
 
 ; THUMB1-LABEL: t6:
-; THUMB1: cmp r{{[0-9]+}}, #0
-; THUMB1: beq
+; THUMB1: subs r1, r0, #1
+; THUMB1: sbcs r0, r1
 
 ; THUMB2-LABEL: t6:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #0
 ; THUMB2: it ne
 ; THUMB2: movne r0, #1
   %tobool = icmp ne i32 %a, 0
   %lnot.ext = zext i1 %tobool to i32

 ; THUMB2-LABEL: t11:
 ; THUMB2: clz r0, r0
 ; THUMB2: lsrs r0, r0, #5
 
 ; V8MBASE-LABEL: t11:
 ; V8MBASE-NOT: movs r0, #0
 ; V8MBASE: movw r0, #40960
 }
+
+define i32 @t12(i32 %a) nounwind {
+entry:
+; ARM-LABEL: t12:
+; ARM-NOT: mov
+; ARM: cmp r0, #0
+; ARM: movne r0, #1
+
+; THUMB1-LABEL: t12:
+; THUMB1: subs r1, r0, #1
+; THUMB1: sbcs r0, r1
+; THUMB1: lsls r0, r0, #1
+
+; THUMB2-LABEL: t12:
+; THUMB2-NOT: mov
+; THUMB2: cmp r0, #0
+; THUMB2: it ne
+; THUMB2: movne r0, #1
+  %tobool = icmp ne i32 %a, 0
+  %lnot.ext = select i1 %tobool, i32 2, i32 0
+  ret i32 %lnot.ext
+}
+
+define i32 @t13(i32 %a) nounwind {
+entry:
+; ARM-LABEL: t13:
+; ARM-NOT: mov
+; ARM: cmp r0, #0
+; ARM: movne r0, #3
+
+; THUMB1-LABEL: t13:
+; THUMB1: cmp r0, #0
+; THUMB1: beq
+; THUMB1: movs r0, #3
+
+; THUMB2-LABEL: t13:
+; THUMB2-NOT: mov
+; THUMB2: cmp r0, #0
+; THUMB2: it ne
+; THUMB2: movne r0, #3
+  %tobool = icmp ne i32 %a, 0
+  %lnot.ext = select i1 %tobool, i32 3, i32 0
+  ret i32 %lnot.ext
+}

llvm/trunk/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=thumb-eabi -mattr=+v6 | FileCheck %s --check-prefixes=THUMBV6
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; THUMBV6-LABEL: muloti_test:
 ; THUMBV6:       @ %bb.0: @ %start
 ; THUMBV6-NEXT:    .save {r4, r5, r6, r7, lr}
 ; THUMBV6-NEXT:    push {r4, r5, r6, r7, lr}
-; THUMBV6-NEXT:    .pad #84
-; THUMBV6-NEXT:    sub sp, #84
-; THUMBV6-NEXT:    mov r6, r3
-; THUMBV6-NEXT:    mov r7, r2
-; THUMBV6-NEXT:    mov r4, r0
+; THUMBV6-NEXT:    .pad #68
+; THUMBV6-NEXT:    sub sp, #68
+; THUMBV6-NEXT:    mov r4, r3
+; THUMBV6-NEXT:    str r2, [sp, #56] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    movs r5, #0
 ; THUMBV6-NEXT:    str r5, [sp, #12]
 ; THUMBV6-NEXT:    str r5, [sp, #8]
-; THUMBV6-NEXT:    ldr r0, [sp, #116]
-; THUMBV6-NEXT:    str r0, [sp, #72] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r0, [sp, #100]
+; THUMBV6-NEXT:    str r0, [sp, #28] @ 4-byte Spill
 ; THUMBV6-NEXT:    str r0, [sp, #4]
-; THUMBV6-NEXT:    ldr r0, [sp, #112]
-; THUMBV6-NEXT:    str r0, [sp, #44] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r0, [sp, #96]
+; THUMBV6-NEXT:    str r0, [sp, #64] @ 4-byte Spill
 ; THUMBV6-NEXT:    str r0, [sp]
 ; THUMBV6-NEXT:    mov r0, r2
 ; THUMBV6-NEXT:    mov r1, r3
 ; THUMBV6-NEXT:    mov r2, r5
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __multi3
-; THUMBV6-NEXT:    str r2, [sp, #36] @ 4-byte Spill
-; THUMBV6-NEXT:    str r3, [sp, #40] @ 4-byte Spill
-; THUMBV6-NEXT:    str r4, [sp, #76] @ 4-byte Spill
-; THUMBV6-NEXT:    stm r4!, {r0, r1}
-; THUMBV6-NEXT:    ldr r4, [sp, #120]
-; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
-; THUMBV6-NEXT:    mov r0, r6
+; THUMBV6-NEXT:    str r2, [sp, #48] @ 4-byte Spill
+; THUMBV6-NEXT:    str r3, [sp, #52] @ 4-byte Spill
+; THUMBV6-NEXT:    str r6, [sp, #44] @ 4-byte Spill
+; THUMBV6-NEXT:    stm r6!, {r0, r1}
+; THUMBV6-NEXT:    ldr r2, [sp, #104]
+; THUMBV6-NEXT:    str r2, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r4
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r4
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    mov r6, r0
-; THUMBV6-NEXT:    str r1, [sp, #48] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r0, [sp, #124]
-; THUMBV6-NEXT:    str r0, [sp, #80] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #36] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r7, r1
+; THUMBV6-NEXT:    subs r0, r1, #1
+; THUMBV6-NEXT:    sbcs r7, r0
+; THUMBV6-NEXT:    ldr r6, [sp, #108]
+; THUMBV6-NEXT:    mov r0, r6
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    ldr r2, [sp, #56] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #24] @ 4-byte Spill
-; THUMBV6-NEXT:    adds r6, r0, r6
-; THUMBV6-NEXT:    str r4, [sp, #68] @ 4-byte Spill
-; THUMBV6-NEXT:    mov r0, r4
+; THUMBV6-NEXT:    subs r2, r1, #1
+; THUMBV6-NEXT:    sbcs r1, r2
+; THUMBV6-NEXT:    subs r2, r4, #1
+; THUMBV6-NEXT:    sbcs r4, r2
+; THUMBV6-NEXT:    str r6, [sp, #40] @ 4-byte Spill
+; THUMBV6-NEXT:    subs r2, r6, #1
+; THUMBV6-NEXT:    sbcs r6, r2
+; THUMBV6-NEXT:    ands r6, r4
+; THUMBV6-NEXT:    orrs r6, r1
+; THUMBV6-NEXT:    orrs r6, r7
+; THUMBV6-NEXT:    ldr r1, [sp, #36] @ 4-byte Reload
+; THUMBV6-NEXT:    adds r4, r0, r1
+; THUMBV6-NEXT:    ldr r0, [sp, #60] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    ldr r2, [sp, #56] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r0, [sp, #20] @ 4-byte Spill
-; THUMBV6-NEXT:    adds r0, r1, r6
-; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #36] @ 4-byte Spill
+; THUMBV6-NEXT:    adds r0, r1, r4
+; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r0, r5
 ; THUMBV6-NEXT:    adcs r0, r5
-; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r4, [sp, #104]
-; THUMBV6-NEXT:    ldr r0, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r0, r6
+; THUMBV6-NEXT:    str r0, [sp, #24] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r4, [sp, #88]
+; THUMBV6-NEXT:    ldr r7, [sp, #28] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r0, r7
 ; THUMBV6-NEXT:    mov r1, r5
 ; THUMBV6-NEXT:    mov r2, r4
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    mov r6, r0
-; THUMBV6-NEXT:    str r1, [sp, #52] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r0, [sp, #108]
-; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #20] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r6, r1
+; THUMBV6-NEXT:    subs r0, r1, #1
+; THUMBV6-NEXT:    sbcs r6, r0
+; THUMBV6-NEXT:    ldr r0, [sp, #92]
+; THUMBV6-NEXT:    str r0, [sp, #56] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    ldr r7, [sp, #44] @ 4-byte Reload
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    ldr r2, [sp, #64] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
-; THUMBV6-NEXT:    adds r6, r0, r6
-; THUMBV6-NEXT:    str r4, [sp, #64] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
+; THUMBV6-NEXT:    subs r2, r1, #1
+; THUMBV6-NEXT:    sbcs r1, r2
+; THUMBV6-NEXT:    subs r2, r7, #1
+; THUMBV6-NEXT:    sbcs r7, r2
+; THUMBV6-NEXT:    mov r3, r7
+; THUMBV6-NEXT:    ldr r7, [sp, #56] @ 4-byte Reload
+; THUMBV6-NEXT:    subs r2, r7, #1
+; THUMBV6-NEXT:    sbcs r7, r2
+; THUMBV6-NEXT:    ands r7, r3
+; THUMBV6-NEXT:    orrs r7, r1
+; THUMBV6-NEXT:    orrs r7, r6
+; THUMBV6-NEXT:    ldr r0, [sp, #20] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r1, [sp, #16] @ 4-byte Reload
+; THUMBV6-NEXT:    adds r6, r1, r0
 ; THUMBV6-NEXT:    mov r0, r4
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    ldr r2, [sp, #64] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    adds r1, r1, r6
 ; THUMBV6-NEXT:    mov r2, r5
 ; THUMBV6-NEXT:    adcs r2, r5
-; THUMBV6-NEXT:    str r2, [sp, #44] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r2, [sp, #20] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r7
+; THUMBV6-NEXT:    ldr r6, [sp, #60] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r3, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r6, r3
+; THUMBV6-NEXT:    subs r3, r6, #1
+; THUMBV6-NEXT:    sbcs r6, r3
+; THUMBV6-NEXT:    ldr r3, [sp, #56] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r4, r3
+; THUMBV6-NEXT:    subs r3, r4, #1
+; THUMBV6-NEXT:    sbcs r4, r3
+; THUMBV6-NEXT:    ands r4, r6
+; THUMBV6-NEXT:    orrs r4, r2
+; THUMBV6-NEXT:    ldr r2, [sp, #24] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r4, r2
+; THUMBV6-NEXT:    ldr r2, [sp, #36] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r0, r2
-; THUMBV6-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r2, [sp, #32] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r1, r2
-; THUMBV6-NEXT:    ldr r2, [sp, #36] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r2, [sp, #48] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r2, r0
-; THUMBV6-NEXT:    ldr r2, [sp, #76] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r2, [sp, #44] @ 4-byte Reload
 ; THUMBV6-NEXT:    str r0, [r2, #8]
-; THUMBV6-NEXT:    ldr r0, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r0, [sp, #52] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r1, r0
 ; THUMBV6-NEXT:    str r1, [r2, #12]
-; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r5, r5
+; THUMBV6-NEXT:    orrs r5, r4
 ; THUMBV6-NEXT:    movs r0, #1
-; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r2, r0
-; THUMBV6-NEXT:    bne .LBB0_2
-; THUMBV6-NEXT:  @ %bb.1: @ %start
-; THUMBV6-NEXT:    mov r2, r1
-; THUMBV6-NEXT:  .LBB0_2: @ %start
-; THUMBV6-NEXT:    str r2, [sp, #40] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r1, [sp, #56] @ 4-byte Reload
-; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r4, r0
-; THUMBV6-NEXT:    bne .LBB0_4
-; THUMBV6-NEXT:  @ %bb.3: @ %start
-; THUMBV6-NEXT:    mov r4, r1
-; THUMBV6-NEXT:  .LBB0_4: @ %start
-; THUMBV6-NEXT:    ldr r1, [sp, #80] @ 4-byte Reload
-; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r2, r0
-; THUMBV6-NEXT:    ldr r3, [sp, #48] @ 4-byte Reload
-; THUMBV6-NEXT:    ldr r7, [sp, #28] @ 4-byte Reload
-; THUMBV6-NEXT:    bne .LBB0_6
-; THUMBV6-NEXT:  @ %bb.5: @ %start
-; THUMBV6-NEXT:    ldr r2, [sp, #80] @ 4-byte Reload
-; THUMBV6-NEXT:  .LBB0_6: @ %start
-; THUMBV6-NEXT:    cmp r3, #0
-; THUMBV6-NEXT:    mov r6, r0
-; THUMBV6-NEXT:    ldr r1, [sp, #72] @ 4-byte Reload
-; THUMBV6-NEXT:    bne .LBB0_8
-; THUMBV6-NEXT:  @ %bb.7: @ %start
-; THUMBV6-NEXT:    mov r6, r3
-; THUMBV6-NEXT:  .LBB0_8: @ %start
-; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
-; THUMBV6-NEXT:    cmp r7, #0
-; THUMBV6-NEXT:    mov r3, r0
-; THUMBV6-NEXT:    bne .LBB0_10
-; THUMBV6-NEXT:  @ %bb.9: @ %start
-; THUMBV6-NEXT:    mov r3, r7
-; THUMBV6-NEXT:  .LBB0_10: @ %start
-; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r7, r1
-; THUMBV6-NEXT:    mov r1, r0
-; THUMBV6-NEXT:    bne .LBB0_12
-; THUMBV6-NEXT:  @ %bb.11: @ %start
-; THUMBV6-NEXT:    mov r1, r7
-; THUMBV6-NEXT:  .LBB0_12: @ %start
-; THUMBV6-NEXT:    ands r2, r4
-; THUMBV6-NEXT:    mov r7, r6
-; THUMBV6-NEXT:    cmp r6, #0
-; THUMBV6-NEXT:    mov r4, r0
-; THUMBV6-NEXT:    bne .LBB0_14
-; THUMBV6-NEXT:  @ %bb.13: @ %start
-; THUMBV6-NEXT:    mov r4, r7
-; THUMBV6-NEXT:  .LBB0_14: @ %start
-; THUMBV6-NEXT:    ldr r6, [sp, #40] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r2, r6
-; THUMBV6-NEXT:    ands r4, r1
-; THUMBV6-NEXT:    orrs r4, r3
-; THUMBV6-NEXT:    ldr r3, [sp, #52] @ 4-byte Reload
-; THUMBV6-NEXT:    cmp r3, #0
-; THUMBV6-NEXT:    mov r1, r0
-; THUMBV6-NEXT:    bne .LBB0_16
-; THUMBV6-NEXT:  @ %bb.15: @ %start
-; THUMBV6-NEXT:    mov r1, r3
-; THUMBV6-NEXT:  .LBB0_16: @ %start
-; THUMBV6-NEXT:    ldr r3, [sp, #56] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r2, r3
-; THUMBV6-NEXT:    orrs r4, r1
-; THUMBV6-NEXT:    ldr r1, [sp, #68] @ 4-byte Reload
-; THUMBV6-NEXT:    ldr r3, [sp, #80] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r1, r3
-; THUMBV6-NEXT:    mov r3, r0
-; THUMBV6-NEXT:    bne .LBB0_18
-; THUMBV6-NEXT:  @ %bb.17: @ %start
-; THUMBV6-NEXT:    mov r3, r1
-; THUMBV6-NEXT:  .LBB0_18: @ %start
-; THUMBV6-NEXT:    ldr r1, [sp, #60] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r2, r1
-; THUMBV6-NEXT:    ldr r1, [sp, #44] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r4, r1
-; THUMBV6-NEXT:    ldr r6, [sp, #64] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r6, r7
-; THUMBV6-NEXT:    mov r1, r0
-; THUMBV6-NEXT:    bne .LBB0_20
-; THUMBV6-NEXT:  @ %bb.19: @ %start
-; THUMBV6-NEXT:    mov r1, r6
-; THUMBV6-NEXT:  .LBB0_20: @ %start
-; THUMBV6-NEXT:    ands r1, r3
-; THUMBV6-NEXT:    orrs r1, r4
-; THUMBV6-NEXT:    orrs r1, r2
-; THUMBV6-NEXT:    orrs r1, r5
-; THUMBV6-NEXT:    ands r1, r0
-; THUMBV6-NEXT:    ldr r0, [sp, #76] @ 4-byte Reload
-; THUMBV6-NEXT:    strb r1, [r0, #16]
-; THUMBV6-NEXT:    add sp, #84
+; THUMBV6-NEXT:    ands r0, r5
+; THUMBV6-NEXT:    strb r0, [r2, #16]
+; THUMBV6-NEXT:    add sp, #68
 ; THUMBV6-NEXT:    pop {r4, r5, r6, r7, pc}
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
   %4 = insertvalue { i128, i8 } undef, i128 %1, 0
   %5 = insertvalue { i128, i8 } %4, i8 %3, 1

llvm/trunk/test/CodeGen/Thumb/umulo-32-legalisation-lowering.ll

 ; RUN: llc < %s -mtriple=thumb-eabi   | FileCheck %s --check-prefixes CHECK,CHECK-LITTLE
 ; RUN: llc < %s -mtriple=thumbeb-eabi | FileCheck %s --check-prefixes CHECK,CHECK-BIG
 
 define i1 @umulo32(i32 %l, i32 %r) unnamed_addr #0 {
 ; CHECK-LABEL: umulo32:
 ; CHECK:                @ %bb.0: @ %start
 ; CHECK-NEXT:           .save {r7, lr}
 ; CHECK-NEXT:           push {r7, lr}
 ; CHECK-LITTLE-NEXT:    movs r2, r1
 ; CHECK-LITTLE-NEXT:    movs r1, #0
 ; CHECK-NEXT:           movs r3, r1
 ; CHECK-BIG-NEXT:       movs r1, r0
 ; CHECK-BIG-NEXT:       movs r0, #0
 ; CHECK-BIG-NEXT:       movs r2, r0
 ; CHECK-NEXT:           bl __aeabi_lmul
-; CHECK-LITTLE-NEXT:    cmp  r1, #0
-; CHECK-LITTLE-NEXT:    bne  .LBB0_2
-; CHECK-LITTLE-NEXT:    @ %bb.1:
 ; CHECK-LITTLE-NEXT:    movs r0, r1
-; CHECK-LITTLE-NEXT:    b    .LBB0_3
-; CHECK-LITTLE-NEXT:    .LBB0_2:
-; CHECK-LITTLE-NEXT:    movs r0, #1
-; CHECK-LITTLE-NEXT:    .LBB0_3:
-; CHECK-BIG-NEXT:       cmp  r0, #0
-; CHECK-BIG-NEXT:       beq  .LBB0_2
-; CHECK-BIG-NEXT:       @ %bb.1:
-; CHECK-BIG-NEXT:       movs r0, #1
-; CHECK-BIG-NEXT:       .LBB0_2:
+; CHECK-LITTLE-NEXT:    subs r1, r1, #1
+; CHECK-BIG-NEXT:       subs r1, r0, #1
+; CHECK-NEXT:           sbcs r0, r1
 ; CHECK-NEXT:           pop {r7}
 ; CHECK-NEXT:           pop {r1}
 ; CHECK-NEXT:           bx r1
 start:
   %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %l, i32 %r) #2
   %1 = extractvalue { i32, i1 } %0, 1
   ret i1 %1
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) #1
 
 attributes #0 = { nounwind readnone uwtable }
 attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { nounwind }