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Differential D59313

[AMDGPU][MC] Corrected checks for DS offset0 range
ClosedPublic

Authored by dp on Mar 13 2019, 11:06 AM.

Details

Reviewers
artem.tamazov
arsenm
Commits
rG04bd1185ade5: [AMDGPU][MC] Corrected checks for DS offset0 range
rL356576: [AMDGPU][MC] Corrected checks for DS offset0 range
Summary

See bug 40889: https://bugs.llvm.org/show_bug.cgi?id=40889

Diff Detail

Event Timeline

dp created this revision.Mar 13 2019, 11:06 AM
Herald added subscribers: t-tye, tpr, dstuttard and 6 others. · View Herald TranscriptMar 13 2019, 11:06 AM
arsenm accepted this revision.Mar 13 2019, 3:04 PM

LGTM

This revision is now accepted and ready to land.Mar 13 2019, 3:04 PM
Closed by commit rL356576: [AMDGPU][MC] Corrected checks for DS offset0 range (authored by dpreobra). · Explain WhyMar 20 2019, 10:14 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMar 20 2019, 10:14 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AsmParser/
2 lines
test/
MC/
AMDGPU/
12 lines

Diff 190455

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

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bool isOff() const { return isImmTy(ImmTyOff); } bool isOff() const { return isImmTy(ImmTyOff); }
bool isExpTgt() const { return isImmTy(ImmTyExpTgt); } bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
bool isExpVM() const { return isImmTy(ImmTyExpVM); } bool isExpVM() const { return isImmTy(ImmTyExpVM); }
bool isExpCompr() const { return isImmTy(ImmTyExpCompr); } bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
bool isOffen() const { return isImmTy(ImmTyOffen); } bool isOffen() const { return isImmTy(ImmTyOffen); }
bool isIdxen() const { return isImmTy(ImmTyIdxen); } bool isIdxen() const { return isImmTy(ImmTyIdxen); }
bool isAddr64() const { return isImmTy(ImmTyAddr64); } bool isAddr64() const { return isImmTy(ImmTyAddr64); }
bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); } bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<16>(getImm()); } bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); } bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); }
bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); } bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); }
bool isGDS() const { return isImmTy(ImmTyGDS); } bool isGDS() const { return isImmTy(ImmTyGDS); }
bool isLDS() const { return isImmTy(ImmTyLDS); } bool isLDS() const { return isImmTy(ImmTyLDS); }
bool isGLC() const { return isImmTy(ImmTyGLC); } bool isGLC() const { return isImmTy(ImmTyGLC); }
bool isSLC() const { return isImmTy(ImmTySLC); } bool isSLC() const { return isImmTy(ImmTySLC); }
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test/MC/AMDGPU/ds-err.s

// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
// offset too big // offset too big
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
ds_add_u32 v2, v4 offset:1000000000 ds_add_u32 v2, v4 offset:1000000000
// offset too big
// CHECK: error: invalid operand for instruction
ds_add_u32 v2, v4 offset:0x10000
// offset0 twice // offset0 twice
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
// offset1 twice // offset1 twice
// CHECK: error: invalid operand for instruction // CHECK: error: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset1:4 offset1:8 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
// offset0 too big // offset0 too big
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset0:1000000000 ds_write2_b32 v2, v4, v6 offset0:1000000000
// offset0 too big
// CHECK: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset0:0x100
// offset1 too big // offset1 too big
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset1:1000000000 ds_write2_b32 v2, v4, v6 offset1:1000000000
// offset1 too big
// CHECK: invalid operand for instruction
ds_write2_b32 v2, v4, v6 offset1:0x100
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// swizzle // swizzle
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CHECK: error: expected a colon // CHECK: error: expected a colon
ds_swizzle_b32 v8, v2 offset ds_swizzle_b32 v8, v2 offset
// CHECK: error: failed parsing operand // CHECK: error: failed parsing operand
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