This patch prevents floating point register constraints in soft float mode.
I really don't like this. It should be possible to mix soft-float, Altivec, VSX, and SPE in the same file using inline asm. I put a check in for SPE codegen specifically to permit inline asm for other floating point models.
What is the motivation for adding this?
I'd like to amend my previous comment: FreeBSD, and I'd guess Linux, too, explicitly builds the kernel with -msoft-float, in order to prevent FPU-consuming optimizations. However, we still need to be able to save and restore FPU context, which requires inline asm (or a completely asm file, not something we want). This change would prevent us being able to do that.
For this example:
int foo ()
double x,y; __asm__ ("fctiw %0,%1" : "=f"(x) : "f"(y)); return x;
clang throws an assert currently for ppc32 soft float. Gcc reports an error similar as in this patch, as well as clang for arm. If I'm wrong with this approach, could you suggest some other solution.
Reading through the diff again, closer, and checking the FreeBSD source, this is acceptable. FreeBSD only uses the base register, and hard-codes register numbers, so doesn't go through float register allocation.
Can you adjust the summary? This doesn't prevent floating point instructions completely, it only prevents floating point register constraints. The assertion that it prevents all floating point instructions is what I first took issue with, so please make it explicit that this is *only* regarding register constraints.