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[AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes
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Authored by dp on Mar 13 2019, 9:49 AM.

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dp created this revision.Mar 13 2019, 9:49 AM

Why is an inline immediate allowed here? I thought these could only be an SGPR or 0

dp added a comment.Mar 14 2019, 3:37 AM

Shader programming documents state that MUBUF SOFFSET is "SGPR to supply unsigned byte offset. Must be an SGPR, M0 or inline constant."
Also note that our tests are based on SP3 tables which also allow inline constants.
Of course, using fp inline constants in this context is meaningless.

In D59305#1428852, @dp wrote:

Shader programming documents state that MUBUF SOFFSET is "SGPR to supply unsigned byte offset. Must be an SGPR, M0 or inline constant."
Also note that our tests are based on SP3 tables which also allow inline constants.
Of course, using fp inline constants in this context is meaningless.

However, assembler can correctly fold the 0x3f000000 constant value into f32 inline constant shown as 0.5 during disassembly.

dp added a comment.Mar 19 2019, 5:48 AM

Could you explain what issues you see in this change? I'm trying to make assembler as close to SP3 as possible.

This revision was not accepted when it landed; it landed in state Needs Review.Mar 27 2019, 6:06 AM
This revision was automatically updated to reflect the committed changes.
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