[ARM] Disable LDM with offset for thumb2 cortex-m cpus

[dmgreen]

Summary

When not optimising for codesize, the extra ADD that can be inserted for the base of an LDM will lead to an extra cycle of latency. Just using LDR's, which are usually pipelined, means fewer total cycles. On Thumb1 cpus, the loads are not pipelined and so it will still be profitable.

This started out as "just turn off the load store optimiser", but has become a little more refined since then. The test case is new, I'm just showing the diff here for clarity.

[t.p.northover]

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

677

I think the check should be optForMinSize. Clang interprets -Os in a more performance-oriented way than GCC; something like "don't needlessly bloat code". -Oz is the real option to squash everything as much as possible.

[dmgreen]

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

677

Sure. This does trade size for performance, in that you will get more LDR's, not turned into a single LDM (plus the ADD). Happy to change that though, the example in the test case ends up using an add.w, so I expect the size differences in many cases will not be very large.

[dmgreen]

Now minsize

[efriedma]

Since we're talking about a Thumb2 core, can we form ldrd here?

[dmgreen]

It may be possibly to create ldrd's, but I don't think that they will be any quicker. An ldrd will take the same time as an ldm (1+N). It could be smaller, depending on whether T1 ldr's are used.

From a quick set of benchmarks I just ran, it looks like on average it did worse with ldrd's than ldr's. Perhaps because of less scheduling freedom?

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

if (Offset == 4 && haveIBAndDA) {
     if (NumRegs <= 2)
       return nullptr;
 
     // On Thumb1, it's not worth materializing a new base register without
     // clobbering the CPSR (i.e. not using ADDS/SUBS).
     if (!SafeToClobberCPSR)
       return nullptr;
 
+    // On M class cores, the extra add will only increase latency
+    if (STI->isMClass() && !isThumb1 && !MF->getFunction().optForMinSize())
+      return nullptr;
+
     unsigned NewBase;
     if (isi32Load(Opcode)) {
       // If it is a load, then just use one of the destination registers
       // as the new base. Will no longer be writeback in Thumb1.
       NewBase = Regs[NumRegs-1].first;
       Writeback = false;
     } else {
       // Find a free register that we can use as scratch register.

llvm/test/CodeGen/Thumb2/ldstopt-addm.ll

 ; CHECK-T1-NEXT:    ldr r0, [r0, #60]
 ; CHECK-T1-NEXT:    adds r0, r3, r0
 ; CHECK-T1-NEXT:    adds r1, r1, r2
 ; CHECK-T1-NEXT:    adds r0, r1, r0
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-LABEL: test:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    add.w r3, r0, #48
-; CHECK-NEXT:    ldm r3, {r1, r2, r3}
+; CHECK-NEXT:    ldr r1, [r0, #48]
+; CHECK-NEXT:    ldr r2, [r0, #52]
+; CHECK-NEXT:    ldr r3, [r0, #56]
 ; CHECK-NEXT:    ldr r0, [r0, #60]
 ; CHECK-NEXT:    add r0, r3
 ; CHECK-NEXT:    add r1, r2
 ; CHECK-NEXT:    add r0, r1
 ; CHECK-NEXT:    bx lr
 entry:
   %gep1 = getelementptr i32, i32* %src, i32 12
   %gep2 = getelementptr i32, i32* %src, i32 13