[MIPS] [microMIPS] Fix PseudoMTLOHI_MM matching and expansion

[mbrkusanin]

Summary

On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless of
+dsp argument. This patch checks is HasDSP predicate is present for
PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate.

Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair.

[atanasyan]

I think we can join D59203 and D59204 patches. Now LLVM incorrectly generates dsp instructions in all cases. After applying D59203 it starts to use PseudoMTLOHI_MM, but test case from the D59204 crashes llc. And after applying the D59204 everything work okay. Let's do an atomic change.

[mbrkusanin]

Combined with it's child revision D59204.

[atanasyan]

We can drop micromips-pseudo-mtlohi-match.ll and keep the micromips-pseudo-mtlohi-expand.ll only because this test checks all that is necessary. With this modification the patch is LGTM.

[mbrkusanin]

Removed micromips-pseudo-mtlohi-match.ll

[mbrkusanin]

Removed micromips 32r6 RUN: line. MTHI and MTLO were removed from micromips R6 so this test is unnecessary.

lib/Target/Mips/MipsDSPInstrInfo.td

 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
 
 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
 
+let AdditionalPredicates = [HasDSP] in {
   def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
+}
 
 // Patterns.
 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
   Pat<pattern, result>, Requires<[pred]>;
 
 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
                     RegisterClass SrcRC> :
    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),

test/CodeGen/Mips/micromips-pseudo-mtlohi-match.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s |\
+; RUN:   FileCheck %s -check-prefixes=MMR2
+; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips < %s |\
+; RUN:   FileCheck %s -check-prefixes=MMR2-DSP
+; RUN: llc -stop-before=expand-isel-pseudos -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s |\
+; RUN:   FileCheck %s -check-prefixes=MMR6
+
+define i64 @test(i32 signext %a, i32 signext %b) {
+  ; MMR2-LABEL: name: test
+  ; MMR2: bb.0.entry:
+  ; MMR2:   liveins: $a0, $a1
+  ; MMR2:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; MMR2:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; MMR2:   [[LI16_MM:%[0-9]+]]:gprmm16 = LI16_MM 0
+  ; MMR2:   [[LI16_MM1:%[0-9]+]]:gprmm16 = LI16_MM 1
+  ; MMR2:   [[PseudoMTLOHI_MM:%[0-9]+]]:acc64 = PseudoMTLOHI_MM killed [[LI16_MM1]], killed [[LI16_MM]]
+  ; MMR2:   [[PseudoMADD_MM:%[0-9]+]]:acc64 = PseudoMADD_MM [[COPY1]], [[COPY]], [[PseudoMTLOHI_MM]]
+  ; MMR2:   [[PseudoMFHI_MM:%[0-9]+]]:gpr32 = PseudoMFHI_MM [[PseudoMADD_MM]]
+  ; MMR2:   [[PseudoMFLO_MM:%[0-9]+]]:gpr32 = PseudoMFLO_MM [[PseudoMADD_MM]]
+  ; MMR2:   $v0 = COPY [[PseudoMFHI_MM]]
+  ; MMR2:   $v1 = COPY [[PseudoMFLO_MM]]
+  ; MMR2:   RetRA implicit $v0, implicit $v1
+  ; MMR2-DSP-LABEL: name: test
+  ; MMR2-DSP: bb.0.entry:
+  ; MMR2-DSP:   liveins: $a0, $a1
+  ; MMR2-DSP:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; MMR2-DSP:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; MMR2-DSP:   [[LI16_MM:%[0-9]+]]:gprmm16 = LI16_MM 0
+  ; MMR2-DSP:   [[LI16_MM1:%[0-9]+]]:gprmm16 = LI16_MM 1
+  ; MMR2-DSP:   [[PseudoMTLOHI_DSP:%[0-9]+]]:acc64dsp = PseudoMTLOHI_DSP killed [[LI16_MM1]], killed [[LI16_MM]]
+  ; MMR2-DSP:   [[MADD_DSP:%[0-9]+]]:acc64dsp = MADD_DSP [[COPY1]], [[COPY]], [[PseudoMTLOHI_DSP]]
+  ; MMR2-DSP:   [[MFHI_DSP:%[0-9]+]]:gpr32 = MFHI_DSP [[MADD_DSP]]
+  ; MMR2-DSP:   [[MFLO_DSP:%[0-9]+]]:gpr32 = MFLO_DSP [[MADD_DSP]]
+  ; MMR2-DSP:   $v0 = COPY [[MFHI_DSP]]
+  ; MMR2-DSP:   $v1 = COPY [[MFLO_DSP]]
+  ; MMR2-DSP:   RetRA implicit $v0, implicit $v1
+  ; MMR6-LABEL: name: test
+  ; MMR6: bb.0.entry:
+  ; MMR6:   liveins: $a0, $a1
+  ; MMR6:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; MMR6:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; MMR6:   [[MUL_MMR6_:%[0-9]+]]:gprmm16 = MUL_MMR6 [[COPY1]], [[COPY]]
+  ; MMR6:   [[ADDIUR2_MM:%[0-9]+]]:gprmm16 = ADDIUR2_MM [[MUL_MMR6_]], 1
+  ; MMR6:   [[SLTu_MM:%[0-9]+]]:gprmm16 = SLTu_MM [[ADDIUR2_MM]], [[MUL_MMR6_]]
+  ; MMR6:   [[MUH_MMR6_:%[0-9]+]]:gprmm16 = MUH_MMR6 [[COPY1]], [[COPY]]
+  ; MMR6:   [[ADDU16_MMR6_:%[0-9]+]]:gprmm16 = ADDU16_MMR6 killed [[MUH_MMR6_]], killed [[SLTu_MM]]
+  ; MMR6:   $v0 = COPY [[ADDU16_MMR6_]]
+  ; MMR6:   $v1 = COPY [[ADDIUR2_MM]]
+  ; MMR6:   RetRA implicit $v0, implicit $v1
+entry:
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %mul = mul nsw i64 %conv, %conv1
+  %add = add nsw i64 %mul, 1
+  ret i64 %add
+}