[mips] Map SW instruction to its microMIPS R6 variant

[atanasyan]

Summary

To provide mapping between standard and microMIPS R6 variants of the sw command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise tablegen starts to show the error Multiple matches found for SW'. After that to restore printing SWSP command as sw`, I add an appropriate MipsInstAlias instance.

We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the micromips-lwsp-swsp.ll test case will be extended.

[Petar.Avramovic]

SWSP instruction has the same encoding for both standard and r6 microMIPS (LOAD_STORE_SP_FM_MM16<0x32>).
If we change SWSP_MM from ISA_MICROMIPS32_NOT_MIPS32R6 to ISA_MICROMIPS, SWSP_MM could be used for R6 size reduction also.
SWSP_MMR6 looks redundant?

[atanasyan]

In D59046#1421451, @Petar.Avramovic wrote:

SWSP instruction has the same encoding for both standard and r6 microMIPS (LOAD_STORE_SP_FM_MM16<0x32>).
If we change SWSP_MM from ISA_MICROMIPS32_NOT_MIPS32R6 to ISA_MICROMIPS, SWSP_MM could be used for R6 size reduction also.
SWSP_MMR6 looks redundant?

There some other places in the code where we emit Mips::SW instruction and rely on mapping provided by td files. For example, expanding ld and sd macros in the MipsAsmParser::expandLoadStoreDMacro; expanding .cprestore in the MipsTargetELFStreamer::emitDirectiveCpRestore. Now LLVM generates incorrect code in these cases. As in the D59045, we can either use td mapping or addd if (MicroMIPS) statements. What approach is better? As to me, I prefer *td* because in that case we keep changes in one place.

[Petar.Avramovic]

I see. I think that in order to keep up with current implementation of microMIPS r6 in MicroMips32r6InstrInfo.td we should map microMIPS instruction to its corresponding standard encoding instruction when necessary.
According to documentation cb e5 has assembler format swsp $ra, 20($sp) but since here both clang and gcc use assembler format sw $ra, 20($sp) I think that we should keep the same behavior.
I would prefer solution in which when target instruction is selected it cannot be changed later. Alternatively for efficiency pseudo instruction could be selected and expanded into target instruction later. This approach would allow faster localization if problem occurs.
Regarding microMIPS r6 implementation I think that we should add both " patterns / manual instruction select" and "instruction mapping" when possible for completeness, since both are present. "Instruction mapping" approach also introduces some code duplication since often there is no difference between microMIPS pre-r6 and r6 instructions.
I agree that mapping in .td file is the best solution here.

[Petar.Avramovic]

LGTM

[atanasyan]

Thanks for the thorough review.

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
                                            store, II_SW, mem_mm_4_lsl2>;
 
 class SWSP_MMR6_DESC
     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
-      MMR6Arch<"sw"> {
+      MMR6Arch<"swsp"> {
   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
   let mayStore = 1;
 }
 
 class JALRC_HB_MMR6_DESC {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins GPR32Opnd:$rs);
   string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");

llvm/lib/Target/Mips/MicroMipsInstrInfo.td

def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
                         LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
                         mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
                         ISA_MICROMIPS32_NOT_MIPS32R6;
 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
                          LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
-def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
+def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
                    ISA_MICROMIPS;
 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
                  ISA_MICROMIPS;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,
                  ISA_MICROMIPS;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;
def : MipsInstAlias<"mfhgc0 $rt, $rs",
                     (MFHGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
                     ISA_MICROMIPS32R5, ASE_VIRT;
 def : MipsInstAlias<"mtgc0 $rt, $rs",
                     (MTGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
                     ISA_MICROMIPS32R5, ASE_VIRT;
 def : MipsInstAlias<"mthgc0 $rt, $rs",
                     (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
                     ISA_MICROMIPS32R5, ASE_VIRT;
+def : MipsInstAlias<"sw $rt, $offset",
+                    (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,
+                    ISA_MICROMIPS;

llvm/lib/Target/Mips/MipsInstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
             MMRel, LW_FM<0x25>, ISA_MIPS1;
   def LW  : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
             LW_FM<0x23>, ISA_MIPS1;
   def SB  : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
             LW_FM<0x28>, ISA_MIPS1;
   def SH  : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
             ISA_MIPS1;
-  def SW  : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
+  def SW  : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
 }
 
 /// load/store left/right
 let AdditionalPredicates = [NotInMicroMips] in {
 def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
           ISA_MIPS1_NOT_32R6_64R6;
 def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
           ISA_MIPS1_NOT_32R6_64R6;

llvm/test/CodeGen/Mips/micromips-sw.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN:     -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN:   | FileCheck --check-prefix=MM2 %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \
+; RUN:     -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN:   | FileCheck --check-prefix=MM6 %s
+
+define void @fun(i32 %val) {
+; MM2-LABEL: fun:
+; MM2:         cb e5 sw $ra, 20($sp)
+
+; MM6-LABEL: fun:
+; MM6:         fb fd 00 14 sw $ra, 20($sp)
+entry:
+  call i32* @fun1()
+  ret void
+}
+
+declare i32* @fun1()