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Differential D59045

[mips] Fix encoding of the `mov.d` command for microMIPS R6
ClosedPublic

Authored by atanasyan on Mar 6 2019, 1:33 PM.

Details

Reviewers
Petar.Avramovic
petarj
sdardis
Commits
rG9bfd140ddb82: [mips] Fix encoding of the `mov.d` command for microMIPS R6
rL356052: [mips] Fix encoding of the `mov.d` command for microMIPS R6
Summary

Before this change LLVM emits non-microMIPS variant of the mov.d command for microMIPS code.

Diff Detail

Repository
rL LLVM

Event Timeline

atanasyan created this revision.Mar 6 2019, 1:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 6 2019, 1:33 PM
Herald added subscribers: jrtc27, hiraditya, arichardson. · View Herald Transcript
Petar.Avramovic added a comment.Mar 7 2019, 2:42 AM

FMOV_D64_MM cannot be selected. Maybe you can do the following change instead in file
/lib/Target/Mips/MipsSEInstrInfo.cpp
line 147:

else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
  Opc = isMicroMips ? Mips::FMOV_D64_MM : Mips::FMOV_D64;
atanasyan updated this revision to Diff 190077.Mar 11 2019, 6:29 AM
  • Select microMIPS R6 variant of the mov.d instruction in the MipsSEInstrInfo::copyPhysReg method.

BTW this variant requires less changes in the source code but I'm concerned a bit that almost all other instructions handled in the MipsSEInstrInfo::copyPhysReg are mapped to their microMIPS counterparts by mappings in the td files.

atanasyan mentioned this in D59046: [mips] Map SW instruction to its microMIPS R6 variant.Mar 11 2019, 8:20 AM
Petar.Avramovic added a comment.Mar 12 2019, 8:49 AM

microMIPS r6 handles float move with FMOV_S_MMR6 instruction mappings in .td file, with that in mind we should do the same with the double move instruction.
Despite the fact that change in /lib/Target/Mips/MipsSEInstrInfo.cpp results in the same output for this test, it should be addressed in another patch. Goal of that patch would be to properly select microMIPS move instruction based on register class used in copy instruction.

Petar.Avramovic accepted this revision.Mar 12 2019, 8:50 AM

LGTM for the initial version of the patch.

This revision is now accepted and ready to land.Mar 12 2019, 8:50 AM
Closed by commit rL356052: [mips] Fix encoding of the `mov.d` command for microMIPS R6 (authored by atanasyan). · Explain WhyMar 13 2019, 7:25 AM
This revision was automatically updated to reflect the committed changes.
atanasyan added a comment.Mar 13 2019, 7:25 AM

Thanks for the thorough review.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
5 lines
3 lines
2 lines
test/
CodeGen/
Mips/
llvm-ir/
162 lines
2 lines
32 lines

Diff 190411

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

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class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
▲ Show 20 Lines • Show All 628 Lines • ▼ Show 20 Linesclass FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
dag InOperandList = (ins SrcRC:$fs); dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
InstrItinClass Itinerary = Itin; InstrItinClass Itinerary = Itin;
Format Form = FrmFR; Format Form = FrmFR;
} }
class FMOV_S_MMR6_DESC class FMOV_S_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>; : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
class FMOV_D_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
class FNEG_S_MMR6_DESC class FNEG_S_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>; : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>, class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
HARDFLOAT; HARDFLOAT;
class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>, class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
HARDFLOAT; HARDFLOAT;
class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>, class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
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def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC, def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC, def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC, def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC, def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC, def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6; def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6; def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6; def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC, def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
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llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td

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} }
multiclass ABSS_MMM<string opstr, InstrItinClass Itin, multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> { SDPatternOperator OpNode = null_frag> {
def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_32 { ISA_MICROMIPS, FGR_32 {
string DecoderNamespace = "MicroMips"; string DecoderNamespace = "MicroMips";
} }
// FIXME: This needs to be part of the instruction mapping tables. def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
ISA_MICROMIPS, FGR_64 { ISA_MICROMIPS, FGR_64 {
string DecoderNamespace = "MicroMipsFP64"; string DecoderNamespace = "MicroMipsFP64";
} }
} }
defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>; defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
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llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Linesclass CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
HARDFLOAT { HARDFLOAT {
let isCommutable = IsComm; let isCommutable = IsComm;
} }
multiclass ABSS_M<string opstr, InstrItinClass Itin, multiclass ABSS_M<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> { SDPatternOperator OpNode= null_frag> {
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
FGR_32; FGR_32;
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
string DecoderNamespace = "MipsFP64"; string DecoderNamespace = "MipsFP64";
} }
} }
multiclass ROUND_M<string opstr, InstrItinClass Itin> { multiclass ROUND_M<string opstr, InstrItinClass Itin> {
def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
let DecoderNamespace = "MipsFP64"; let DecoderNamespace = "MipsFP64";
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llvm/trunk/test/CodeGen/Mips/llvm-ir/fptosi.ll

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; RUN: FileCheck %s -check-prefixes=MMR6-SF ; RUN: FileCheck %s -check-prefixes=MMR6-SF
; Test that fptosi can be matched for MIPS targets for various FPU ; Test that fptosi can be matched for MIPS targets for various FPU
; configurations ; configurations
define i32 @test1(float %t) { define i32 @test1(float %t) {
; M32-LABEL: test1: ; M32-LABEL: test1:
; M32: # %bb.0: # %entry ; M32: # %bb.0: # %entry
; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M32-NEXT: # <MCOperand Reg:147> ; M32-NEXT: # <MCOperand Reg:147>
; M32-NEXT: # <MCOperand Reg:159>> ; M32-NEXT: # <MCOperand Reg:159>>
; M32-NEXT: jr $ra # <MCInst #1628 JR ; M32-NEXT: jr $ra # <MCInst #1629 JR
; M32-NEXT: # <MCOperand Reg:19>> ; M32-NEXT: # <MCOperand Reg:19>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32-NEXT: # <MCOperand Reg:321> ; M32-NEXT: # <MCOperand Reg:321>
; M32-NEXT: # <MCOperand Reg:147>> ; M32-NEXT: # <MCOperand Reg:147>>
; ;
; M32R2-FP64-LABEL: test1: ; M32R2-FP64-LABEL: test1:
; M32R2-FP64: # %bb.0: # %entry ; M32R2-FP64: # %bb.0: # %entry
; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M32R2-FP64-NEXT: # <MCOperand Reg:147> ; M32R2-FP64-NEXT: # <MCOperand Reg:147>
; M32R2-FP64-NEXT: # <MCOperand Reg:159>> ; M32R2-FP64-NEXT: # <MCOperand Reg:159>>
; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR ; M32R2-FP64-NEXT: jr $ra # <MCInst #1629 JR
; M32R2-FP64-NEXT: # <MCOperand Reg:19>> ; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R2-FP64-NEXT: # <MCOperand Reg:321> ; M32R2-FP64-NEXT: # <MCOperand Reg:321>
; M32R2-FP64-NEXT: # <MCOperand Reg:147>> ; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
; ;
; M32R2-SF-LABEL: test1: ; M32R2-SF-LABEL: test1:
; M32R2-SF: # %bb.0: # %entry ; M32R2-SF: # %bb.0: # %entry
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>> ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; M32R2-SF-NEXT: # <MCInst #2519 SW ; M32R2-SF-NEXT: # <MCInst #2520 SW
; M32R2-SF-NEXT: # <MCOperand Reg:19> ; M32R2-SF-NEXT: # <MCOperand Reg:19>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:20>> ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4 ; M32R2-SF-NEXT: .cfi_offset 31, -4
; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #1606 JAL ; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #1607 JAL
; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>> ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
; M32R2-SF-NEXT: nop # <MCInst #2370 SLL ; M32R2-SF-NEXT: nop # <MCInst #2371 SLL
; M32R2-SF-NEXT: # <MCOperand Reg:21> ; M32R2-SF-NEXT: # <MCOperand Reg:21>
; M32R2-SF-NEXT: # <MCOperand Reg:21> ; M32R2-SF-NEXT: # <MCOperand Reg:21>
; M32R2-SF-NEXT: # <MCOperand Imm:0>> ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; M32R2-SF-NEXT: # <MCInst #1722 LW ; M32R2-SF-NEXT: # <MCInst #1723 LW
; M32R2-SF-NEXT: # <MCOperand Reg:19> ; M32R2-SF-NEXT: # <MCOperand Reg:19>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:20>> ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR ; M32R2-SF-NEXT: jr $ra # <MCInst #1629 JR
; M32R2-SF-NEXT: # <MCOperand Reg:19>> ; M32R2-SF-NEXT: # <MCOperand Reg:19>>
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:24>> ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
; ;
; M32R3R5-LABEL: test1: ; M32R3R5-LABEL: test1:
; M32R3R5: # %bb.0: # %entry ; M32R3R5: # %bb.0: # %entry
; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M32R3R5-NEXT: # <MCOperand Reg:147> ; M32R3R5-NEXT: # <MCOperand Reg:147>
; M32R3R5-NEXT: # <MCOperand Reg:159>> ; M32R3R5-NEXT: # <MCOperand Reg:159>>
; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR ; M32R3R5-NEXT: jr $ra # <MCInst #1629 JR
; M32R3R5-NEXT: # <MCOperand Reg:19>> ; M32R3R5-NEXT: # <MCOperand Reg:19>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R3R5-NEXT: # <MCOperand Reg:321> ; M32R3R5-NEXT: # <MCOperand Reg:321>
; M32R3R5-NEXT: # <MCOperand Reg:147>> ; M32R3R5-NEXT: # <MCOperand Reg:147>>
; ;
; M32R6-LABEL: test1: ; M32R6-LABEL: test1:
; M32R6: # %bb.0: # %entry ; M32R6: # %bb.0: # %entry
; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M32R6-NEXT: # <MCOperand Reg:147> ; M32R6-NEXT: # <MCOperand Reg:147>
; M32R6-NEXT: # <MCOperand Reg:159>> ; M32R6-NEXT: # <MCOperand Reg:159>>
; M32R6-NEXT: jr $ra # <MCInst #1607 JALR ; M32R6-NEXT: jr $ra # <MCInst #1608 JALR
; M32R6-NEXT: # <MCOperand Reg:21> ; M32R6-NEXT: # <MCOperand Reg:21>
; M32R6-NEXT: # <MCOperand Reg:19>> ; M32R6-NEXT: # <MCOperand Reg:19>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R6-NEXT: # <MCOperand Reg:321> ; M32R6-NEXT: # <MCOperand Reg:321>
; M32R6-NEXT: # <MCOperand Reg:147>> ; M32R6-NEXT: # <MCOperand Reg:147>>
; ;
; M64-LABEL: test1: ; M64-LABEL: test1:
; M64: # %bb.0: # %entry ; M64: # %bb.0: # %entry
; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M64-NEXT: # <MCOperand Reg:147> ; M64-NEXT: # <MCOperand Reg:147>
; M64-NEXT: # <MCOperand Reg:159>> ; M64-NEXT: # <MCOperand Reg:159>>
; M64-NEXT: jr $ra # <MCInst #1628 JR ; M64-NEXT: jr $ra # <MCInst #1629 JR
; M64-NEXT: # <MCOperand Reg:301>> ; M64-NEXT: # <MCOperand Reg:301>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M64-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M64-NEXT: # <MCOperand Reg:321> ; M64-NEXT: # <MCOperand Reg:321>
; M64-NEXT: # <MCOperand Reg:147>> ; M64-NEXT: # <MCOperand Reg:147>>
; ;
; M64R6-LABEL: test1: ; M64R6-LABEL: test1:
; M64R6: # %bb.0: # %entry ; M64R6: # %bb.0: # %entry
; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2637 TRUNC_W_S ; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S
; M64R6-NEXT: # <MCOperand Reg:147> ; M64R6-NEXT: # <MCOperand Reg:147>
; M64R6-NEXT: # <MCOperand Reg:159>> ; M64R6-NEXT: # <MCOperand Reg:159>>
; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64 ; M64R6-NEXT: jr $ra # <MCInst #1610 JALR64
; M64R6-NEXT: # <MCOperand Reg:355> ; M64R6-NEXT: # <MCOperand Reg:355>
; M64R6-NEXT: # <MCOperand Reg:301>> ; M64R6-NEXT: # <MCOperand Reg:301>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M64R6-NEXT: # <MCOperand Reg:321> ; M64R6-NEXT: # <MCOperand Reg:321>
; M64R6-NEXT: # <MCOperand Reg:147>> ; M64R6-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-FP32-LABEL: test1: ; MMR2-FP32-LABEL: test1:
; MMR2-FP32: # %bb.0: # %entry ; MMR2-FP32: # %bb.0: # %entry
; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM ; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:147> ; MMR2-FP32-NEXT: # <MCOperand Reg:147>
; MMR2-FP32-NEXT: # <MCOperand Reg:159>> ; MMR2-FP32-NEXT: # <MCOperand Reg:159>>
; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM ; MMR2-FP32-NEXT: jr $ra # <MCInst #1640 JR_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:19>> ; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:321> ; MMR2-FP32-NEXT: # <MCOperand Reg:321>
; MMR2-FP32-NEXT: # <MCOperand Reg:147>> ; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-FP64-LABEL: test1: ; MMR2-FP64-LABEL: test1:
; MMR2-FP64: # %bb.0: # %entry ; MMR2-FP64: # %bb.0: # %entry
; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2638 TRUNC_W_S_MM ; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:147> ; MMR2-FP64-NEXT: # <MCOperand Reg:147>
; MMR2-FP64-NEXT: # <MCOperand Reg:159>> ; MMR2-FP64-NEXT: # <MCOperand Reg:159>>
; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM ; MMR2-FP64-NEXT: jr $ra # <MCInst #1640 JR_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:19>> ; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:321> ; MMR2-FP64-NEXT: # <MCOperand Reg:321>
; MMR2-FP64-NEXT: # <MCOperand Reg:147>> ; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-SF-LABEL: test1: ; MMR2-SF-LABEL: test1:
; MMR2-SF: # %bb.0: # %entry ; MMR2-SF: # %bb.0: # %entry
; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM ; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:-24>> ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM ; MMR2-SF-NEXT: # <MCInst #2548 SWSP_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19> ; MMR2-SF-NEXT: # <MCOperand Reg:19>
; MMR2-SF-NEXT: # <MCOperand Reg:20> ; MMR2-SF-NEXT: # <MCOperand Reg:20>
; MMR2-SF-NEXT: # <MCOperand Imm:20>> ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4 ; MMR2-SF-NEXT: .cfi_offset 31, -4
; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #1621 JAL_MM ; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #1622 JAL_MM
; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>> ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
; MMR2-SF-NEXT: nop # <MCInst #2370 SLL ; MMR2-SF-NEXT: nop # <MCInst #2371 SLL
; MMR2-SF-NEXT: # <MCOperand Reg:21> ; MMR2-SF-NEXT: # <MCOperand Reg:21>
; MMR2-SF-NEXT: # <MCOperand Reg:21> ; MMR2-SF-NEXT: # <MCOperand Reg:21>
; MMR2-SF-NEXT: # <MCOperand Imm:0>> ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM ; MMR2-SF-NEXT: # <MCInst #1753 LWSP_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19> ; MMR2-SF-NEXT: # <MCOperand Reg:19>
; MMR2-SF-NEXT: # <MCOperand Reg:20> ; MMR2-SF-NEXT: # <MCOperand Reg:20>
; MMR2-SF-NEXT: # <MCOperand Imm:20>> ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM ; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>> ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR2-SF-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19>> ; MMR2-SF-NEXT: # <MCOperand Reg:19>>
; ;
; MMR6-LABEL: test1: ; MMR6-LABEL: test1:
; MMR6: # %bb.0: # %entry ; MMR6: # %bb.0: # %entry
; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2639 TRUNC_W_S_MMR6 ; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #2640 TRUNC_W_S_MMR6
; MMR6-NEXT: # <MCOperand Reg:147> ; MMR6-NEXT: # <MCOperand Reg:147>
; MMR6-NEXT: # <MCOperand Reg:159>> ; MMR6-NEXT: # <MCOperand Reg:159>>
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR6-NEXT: # <MCOperand Reg:321> ; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:147>> ; MMR6-NEXT: # <MCOperand Reg:147>>
; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR6-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>> ; MMR6-NEXT: # <MCOperand Reg:19>>
; ;
; MMR6-SF-LABEL: test1: ; MMR6-SF-LABEL: test1:
; MMR6-SF: # %bb.0: # %entry ; MMR6-SF: # %bb.0: # %entry
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>> ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR6-SF-NEXT: # <MCInst #2519 SW ; MMR6-SF-NEXT: # <MCInst #2520 SW
; MMR6-SF-NEXT: # <MCOperand Reg:19> ; MMR6-SF-NEXT: # <MCOperand Reg:19>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4 ; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #1610 JALRC16_MMR6 ; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #1611 JALRC16_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>> ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #1722 LW ; MMR6-SF-NEXT: # <MCInst #1723 LW
; MMR6-SF-NEXT: # <MCOperand Reg:19> ; MMR6-SF-NEXT: # <MCOperand Reg:19>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:24>> ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR6-SF-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR6-SF-NEXT: # <MCOperand Reg:19>> ; MMR6-SF-NEXT: # <MCOperand Reg:19>>
entry: entry:
%conv = fptosi float %t to i32 %conv = fptosi float %t to i32
ret i32 %conv ret i32 %conv
} }
define i32 @test2(double %t) { define i32 @test2(double %t) {
; M32-LABEL: test2: ; M32-LABEL: test2:
; M32: # %bb.0: # %entry ; M32: # %bb.0: # %entry
; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32 ; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
; M32-NEXT: # <MCOperand Reg:147> ; M32-NEXT: # <MCOperand Reg:147>
; M32-NEXT: # <MCOperand Reg:133>> ; M32-NEXT: # <MCOperand Reg:133>>
; M32-NEXT: jr $ra # <MCInst #1628 JR ; M32-NEXT: jr $ra # <MCInst #1629 JR
; M32-NEXT: # <MCOperand Reg:19>> ; M32-NEXT: # <MCOperand Reg:19>>
; M32-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32-NEXT: # <MCOperand Reg:321> ; M32-NEXT: # <MCOperand Reg:321>
; M32-NEXT: # <MCOperand Reg:147>> ; M32-NEXT: # <MCOperand Reg:147>>
; ;
; M32R2-FP64-LABEL: test2: ; M32R2-FP64-LABEL: test2:
; M32R2-FP64: # %bb.0: # %entry ; M32R2-FP64: # %bb.0: # %entry
; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64 ; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
; M32R2-FP64-NEXT: # <MCOperand Reg:147> ; M32R2-FP64-NEXT: # <MCOperand Reg:147>
; M32R2-FP64-NEXT: # <MCOperand Reg:373>> ; M32R2-FP64-NEXT: # <MCOperand Reg:373>>
; M32R2-FP64-NEXT: jr $ra # <MCInst #1628 JR ; M32R2-FP64-NEXT: jr $ra # <MCInst #1629 JR
; M32R2-FP64-NEXT: # <MCOperand Reg:19>> ; M32R2-FP64-NEXT: # <MCOperand Reg:19>>
; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R2-FP64-NEXT: # <MCOperand Reg:321> ; M32R2-FP64-NEXT: # <MCOperand Reg:321>
; M32R2-FP64-NEXT: # <MCOperand Reg:147>> ; M32R2-FP64-NEXT: # <MCOperand Reg:147>>
; ;
; M32R2-SF-LABEL: test2: ; M32R2-SF-LABEL: test2:
; M32R2-SF: # %bb.0: # %entry ; M32R2-SF: # %bb.0: # %entry
; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>> ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; M32R2-SF-NEXT: # <MCInst #2519 SW ; M32R2-SF-NEXT: # <MCInst #2520 SW
; M32R2-SF-NEXT: # <MCOperand Reg:19> ; M32R2-SF-NEXT: # <MCOperand Reg:19>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:20>> ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4 ; M32R2-SF-NEXT: .cfi_offset 31, -4
; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #1606 JAL ; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #1607 JAL
; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>> ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
; M32R2-SF-NEXT: nop # <MCInst #2370 SLL ; M32R2-SF-NEXT: nop # <MCInst #2371 SLL
; M32R2-SF-NEXT: # <MCOperand Reg:21> ; M32R2-SF-NEXT: # <MCOperand Reg:21>
; M32R2-SF-NEXT: # <MCOperand Reg:21> ; M32R2-SF-NEXT: # <MCOperand Reg:21>
; M32R2-SF-NEXT: # <MCOperand Imm:0>> ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; M32R2-SF-NEXT: # <MCInst #1722 LW ; M32R2-SF-NEXT: # <MCInst #1723 LW
; M32R2-SF-NEXT: # <MCOperand Reg:19> ; M32R2-SF-NEXT: # <MCOperand Reg:19>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:20>> ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: jr $ra # <MCInst #1628 JR ; M32R2-SF-NEXT: jr $ra # <MCInst #1629 JR
; M32R2-SF-NEXT: # <MCOperand Reg:19>> ; M32R2-SF-NEXT: # <MCOperand Reg:19>>
; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Reg:20> ; M32R2-SF-NEXT: # <MCOperand Reg:20>
; M32R2-SF-NEXT: # <MCOperand Imm:24>> ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
; ;
; M32R3R5-LABEL: test2: ; M32R3R5-LABEL: test2:
; M32R3R5: # %bb.0: # %entry ; M32R3R5: # %bb.0: # %entry
; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #2633 TRUNC_W_D32 ; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D32
; M32R3R5-NEXT: # <MCOperand Reg:147> ; M32R3R5-NEXT: # <MCOperand Reg:147>
; M32R3R5-NEXT: # <MCOperand Reg:133>> ; M32R3R5-NEXT: # <MCOperand Reg:133>>
; M32R3R5-NEXT: jr $ra # <MCInst #1628 JR ; M32R3R5-NEXT: jr $ra # <MCInst #1629 JR
; M32R3R5-NEXT: # <MCOperand Reg:19>> ; M32R3R5-NEXT: # <MCOperand Reg:19>>
; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R3R5-NEXT: # <MCOperand Reg:321> ; M32R3R5-NEXT: # <MCOperand Reg:321>
; M32R3R5-NEXT: # <MCOperand Reg:147>> ; M32R3R5-NEXT: # <MCOperand Reg:147>>
; ;
; M32R6-LABEL: test2: ; M32R6-LABEL: test2:
; M32R6: # %bb.0: # %entry ; M32R6: # %bb.0: # %entry
; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64 ; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
; M32R6-NEXT: # <MCOperand Reg:147> ; M32R6-NEXT: # <MCOperand Reg:147>
; M32R6-NEXT: # <MCOperand Reg:373>> ; M32R6-NEXT: # <MCOperand Reg:373>>
; M32R6-NEXT: jr $ra # <MCInst #1607 JALR ; M32R6-NEXT: jr $ra # <MCInst #1608 JALR
; M32R6-NEXT: # <MCOperand Reg:21> ; M32R6-NEXT: # <MCOperand Reg:21>
; M32R6-NEXT: # <MCOperand Reg:19>> ; M32R6-NEXT: # <MCOperand Reg:19>>
; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M32R6-NEXT: # <MCOperand Reg:321> ; M32R6-NEXT: # <MCOperand Reg:321>
; M32R6-NEXT: # <MCOperand Reg:147>> ; M32R6-NEXT: # <MCOperand Reg:147>>
; ;
; M64-LABEL: test2: ; M64-LABEL: test2:
; M64: # %bb.0: # %entry ; M64: # %bb.0: # %entry
; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64 ; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
; M64-NEXT: # <MCOperand Reg:147> ; M64-NEXT: # <MCOperand Reg:147>
; M64-NEXT: # <MCOperand Reg:373>> ; M64-NEXT: # <MCOperand Reg:373>>
; M64-NEXT: jr $ra # <MCInst #1628 JR ; M64-NEXT: jr $ra # <MCInst #1629 JR
; M64-NEXT: # <MCOperand Reg:301>> ; M64-NEXT: # <MCOperand Reg:301>>
; M64-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M64-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M64-NEXT: # <MCOperand Reg:321> ; M64-NEXT: # <MCOperand Reg:321>
; M64-NEXT: # <MCOperand Reg:147>> ; M64-NEXT: # <MCOperand Reg:147>>
; ;
; M64R6-LABEL: test2: ; M64R6-LABEL: test2:
; M64R6: # %bb.0: # %entry ; M64R6: # %bb.0: # %entry
; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2634 TRUNC_W_D64 ; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D64
; M64R6-NEXT: # <MCOperand Reg:147> ; M64R6-NEXT: # <MCOperand Reg:147>
; M64R6-NEXT: # <MCOperand Reg:373>> ; M64R6-NEXT: # <MCOperand Reg:373>>
; M64R6-NEXT: jr $ra # <MCInst #1609 JALR64 ; M64R6-NEXT: jr $ra # <MCInst #1610 JALR64
; M64R6-NEXT: # <MCOperand Reg:355> ; M64R6-NEXT: # <MCOperand Reg:355>
; M64R6-NEXT: # <MCOperand Reg:301>> ; M64R6-NEXT: # <MCOperand Reg:301>>
; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1837 MFC1 ; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #1838 MFC1
; M64R6-NEXT: # <MCOperand Reg:321> ; M64R6-NEXT: # <MCOperand Reg:321>
; M64R6-NEXT: # <MCOperand Reg:147>> ; M64R6-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-FP32-LABEL: test2: ; MMR2-FP32-LABEL: test2:
; MMR2-FP32: # %bb.0: # %entry ; MMR2-FP32: # %bb.0: # %entry
; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_MM ; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #2637 TRUNC_W_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:147> ; MMR2-FP32-NEXT: # <MCOperand Reg:147>
; MMR2-FP32-NEXT: # <MCOperand Reg:133>> ; MMR2-FP32-NEXT: # <MCOperand Reg:133>>
; MMR2-FP32-NEXT: jr $ra # <MCInst #1639 JR_MM ; MMR2-FP32-NEXT: jr $ra # <MCInst #1640 JR_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:19>> ; MMR2-FP32-NEXT: # <MCOperand Reg:19>>
; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR2-FP32-NEXT: # <MCOperand Reg:321> ; MMR2-FP32-NEXT: # <MCOperand Reg:321>
; MMR2-FP32-NEXT: # <MCOperand Reg:147>> ; MMR2-FP32-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-FP64-LABEL: test2: ; MMR2-FP64-LABEL: test2:
; MMR2-FP64: # %bb.0: # %entry ; MMR2-FP64: # %bb.0: # %entry
; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM ; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #1097 CVT_W_D64_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:147> ; MMR2-FP64-NEXT: # <MCOperand Reg:147>
; MMR2-FP64-NEXT: # <MCOperand Reg:373>> ; MMR2-FP64-NEXT: # <MCOperand Reg:373>>
; MMR2-FP64-NEXT: jr $ra # <MCInst #1639 JR_MM ; MMR2-FP64-NEXT: jr $ra # <MCInst #1640 JR_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:19>> ; MMR2-FP64-NEXT: # <MCOperand Reg:19>>
; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR2-FP64-NEXT: # <MCOperand Reg:321> ; MMR2-FP64-NEXT: # <MCOperand Reg:321>
; MMR2-FP64-NEXT: # <MCOperand Reg:147>> ; MMR2-FP64-NEXT: # <MCOperand Reg:147>>
; ;
; MMR2-SF-LABEL: test2: ; MMR2-SF-LABEL: test2:
; MMR2-SF: # %bb.0: # %entry ; MMR2-SF: # %bb.0: # %entry
; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM ; MMR2-SF-NEXT: addiusp -24 # <MCInst #561 ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:-24>> ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR2-SF-NEXT: # <MCInst #2547 SWSP_MM ; MMR2-SF-NEXT: # <MCInst #2548 SWSP_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19> ; MMR2-SF-NEXT: # <MCOperand Reg:19>
; MMR2-SF-NEXT: # <MCOperand Reg:20> ; MMR2-SF-NEXT: # <MCOperand Reg:20>
; MMR2-SF-NEXT: # <MCOperand Imm:20>> ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4 ; MMR2-SF-NEXT: .cfi_offset 31, -4
; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #1621 JAL_MM ; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #1622 JAL_MM
; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>> ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
; MMR2-SF-NEXT: nop # <MCInst #2370 SLL ; MMR2-SF-NEXT: nop # <MCInst #2371 SLL
; MMR2-SF-NEXT: # <MCOperand Reg:21> ; MMR2-SF-NEXT: # <MCOperand Reg:21>
; MMR2-SF-NEXT: # <MCOperand Reg:21> ; MMR2-SF-NEXT: # <MCOperand Reg:21>
; MMR2-SF-NEXT: # <MCOperand Imm:0>> ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR2-SF-NEXT: # <MCInst #1752 LWSP_MM ; MMR2-SF-NEXT: # <MCInst #1753 LWSP_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19> ; MMR2-SF-NEXT: # <MCOperand Reg:19>
; MMR2-SF-NEXT: # <MCOperand Reg:20> ; MMR2-SF-NEXT: # <MCOperand Reg:20>
; MMR2-SF-NEXT: # <MCOperand Imm:20>> ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM ; MMR2-SF-NEXT: addiusp 24 # <MCInst #561 ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>> ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
; MMR2-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR2-SF-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR2-SF-NEXT: # <MCOperand Reg:19>> ; MMR2-SF-NEXT: # <MCOperand Reg:19>>
; ;
; MMR6-LABEL: test2: ; MMR6-LABEL: test2:
; MMR6: # %bb.0: # %entry ; MMR6: # %bb.0: # %entry
; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2635 TRUNC_W_D_MMR6 ; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #2636 TRUNC_W_D_MMR6
; MMR6-NEXT: # <MCOperand Reg:147> ; MMR6-NEXT: # <MCOperand Reg:147>
; MMR6-NEXT: # <MCOperand Reg:373>> ; MMR6-NEXT: # <MCOperand Reg:373>>
; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1839 MFC1_MM ; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #1840 MFC1_MM
; MMR6-NEXT: # <MCOperand Reg:321> ; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:147>> ; MMR6-NEXT: # <MCOperand Reg:147>>
; MMR6-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR6-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>> ; MMR6-NEXT: # <MCOperand Reg:19>>
; ;
; MMR6-SF-LABEL: test2: ; MMR6-SF-LABEL: test2:
; MMR6-SF: # %bb.0: # %entry ; MMR6-SF: # %bb.0: # %entry
; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #624 ADDiu
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>> ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MMR6-SF-NEXT: # <MCInst #2519 SW ; MMR6-SF-NEXT: # <MCInst #2520 SW
; MMR6-SF-NEXT: # <MCOperand Reg:19> ; MMR6-SF-NEXT: # <MCOperand Reg:19>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4 ; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #1610 JALRC16_MMR6 ; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #1611 JALRC16_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>> ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #1722 LW ; MMR6-SF-NEXT: # <MCInst #1723 LW
; MMR6-SF-NEXT: # <MCOperand Reg:19> ; MMR6-SF-NEXT: # <MCOperand Reg:19>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:20>> ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #624 ADDiu
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Reg:20> ; MMR6-SF-NEXT: # <MCOperand Reg:20>
; MMR6-SF-NEXT: # <MCOperand Imm:24>> ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
; MMR6-SF-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR6-SF-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR6-SF-NEXT: # <MCOperand Reg:19>> ; MMR6-SF-NEXT: # <MCOperand Reg:19>>
entry: entry:
%conv = fptosi double %t to i32 %conv = fptosi double %t to i32
ret i32 %conv ret i32 %conv
} }

llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll

Show All 17 Lines
; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A] ; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A]
; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1
; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00] ; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00]
; MM2-NEXT: $BB0_2: # %return ; MM2-NEXT: $BB0_2: # %return
; MM2-NEXT: jrc $ra # encoding: [0x45,0xbf] ; MM2-NEXT: jrc $ra # encoding: [0x45,0xbf]
; ;
; MM6-LABEL: foo: ; MM6-LABEL: foo:
; MM6: # %bb.0: # %entry ; MM6: # %bb.0: # %entry
; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06] ; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b]
; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b] ; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b]
; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b] ; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b]
; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5] ; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5]
; MM6-NEXT: mfc1 $2, $f1 # encoding: [0x54,0x41,0x20,0x3b] ; MM6-NEXT: mfc1 $2, $f1 # encoding: [0x54,0x41,0x20,0x3b]
; MM6-NEXT: andi16 $2, $2, 1 # encoding: [0x2d,0x21] ; MM6-NEXT: andi16 $2, $2, 1 # encoding: [0x2d,0x21]
; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf] ; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf]
entry: entry:
%cmp = fcmp ogt double %a, 0.000000e+00 %cmp = fcmp ogt double %a, 0.000000e+00
Show All 33 Lines

llvm/trunk/test/CodeGen/Mips/micromips-pseudo-mtlohi-expand.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\ ; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\
; RUN: FileCheck %s -check-prefixes=MMR2 ; RUN: FileCheck %s -check-prefixes=MMR2
; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\ ; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\
; RUN: FileCheck %s -check-prefixes=MMR2-DSP ; RUN: FileCheck %s -check-prefixes=MMR2-DSP
define i64 @test(i32 signext %a, i32 signext %b) { define i64 @test(i32 signext %a, i32 signext %b) {
; MMR2-LABEL: test: ; MMR2-LABEL: test:
; MMR2: # %bb.0: # %entry ; MMR2: # %bb.0: # %entry
; MMR2-NEXT: li16 $2, 0 # <MCInst #1700 LI16_MM ; MMR2-NEXT: li16 $2, 0 # <MCInst #1701 LI16_MM
; MMR2-NEXT: # <MCOperand Reg:321> ; MMR2-NEXT: # <MCOperand Reg:321>
; MMR2-NEXT: # <MCOperand Imm:0>> ; MMR2-NEXT: # <MCOperand Imm:0>>
; MMR2-NEXT: li16 $3, 1 # <MCInst #1700 LI16_MM ; MMR2-NEXT: li16 $3, 1 # <MCInst #1701 LI16_MM
; MMR2-NEXT: # <MCOperand Reg:322> ; MMR2-NEXT: # <MCOperand Reg:322>
; MMR2-NEXT: # <MCOperand Imm:1>> ; MMR2-NEXT: # <MCOperand Imm:1>>
; MMR2-NEXT: mtlo $3 # <MCInst #2008 MTLO_MM ; MMR2-NEXT: mtlo $3 # <MCInst #2009 MTLO_MM
; MMR2-NEXT: # <MCOperand Reg:322>> ; MMR2-NEXT: # <MCOperand Reg:322>>
; MMR2-NEXT: mthi $2 # <MCInst #2001 MTHI_MM ; MMR2-NEXT: mthi $2 # <MCInst #2002 MTHI_MM
; MMR2-NEXT: # <MCOperand Reg:321>> ; MMR2-NEXT: # <MCOperand Reg:321>>
; MMR2-NEXT: madd $4, $5 # <MCInst #1774 MADD ; MMR2-NEXT: madd $4, $5 # <MCInst #1775 MADD
; MMR2-NEXT: # <MCOperand Reg:22> ; MMR2-NEXT: # <MCOperand Reg:22>
; MMR2-NEXT: # <MCOperand Reg:23>> ; MMR2-NEXT: # <MCOperand Reg:23>>
; MMR2-NEXT: mflo16 $2 # <MCInst #1860 MFLO16_MM ; MMR2-NEXT: mflo16 $2 # <MCInst #1861 MFLO16_MM
; MMR2-NEXT: # <MCOperand Reg:321>> ; MMR2-NEXT: # <MCOperand Reg:321>>
; MMR2-NEXT: mfhi16 $3 # <MCInst #1854 MFHI16_MM ; MMR2-NEXT: mfhi16 $3 # <MCInst #1855 MFHI16_MM
; MMR2-NEXT: # <MCOperand Reg:322>> ; MMR2-NEXT: # <MCOperand Reg:322>>
; MMR2-NEXT: jrc $ra # <MCInst #1632 JRC16_MM ; MMR2-NEXT: jrc $ra # <MCInst #1633 JRC16_MM
; MMR2-NEXT: # <MCOperand Reg:19>> ; MMR2-NEXT: # <MCOperand Reg:19>>
; ;
; MMR2-DSP-LABEL: test: ; MMR2-DSP-LABEL: test:
; MMR2-DSP: # %bb.0: # %entry ; MMR2-DSP: # %bb.0: # %entry
; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #1700 LI16_MM ; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #1701 LI16_MM
; MMR2-DSP-NEXT: # <MCOperand Reg:321> ; MMR2-DSP-NEXT: # <MCOperand Reg:321>
; MMR2-DSP-NEXT: # <MCOperand Imm:0>> ; MMR2-DSP-NEXT: # <MCOperand Imm:0>>
; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #1700 LI16_MM ; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #1701 LI16_MM
; MMR2-DSP-NEXT: # <MCOperand Reg:322> ; MMR2-DSP-NEXT: # <MCOperand Reg:322>
; MMR2-DSP-NEXT: # <MCOperand Imm:1>> ; MMR2-DSP-NEXT: # <MCOperand Imm:1>>
; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #2006 MTLO_DSP ; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #2007 MTLO_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:291> ; MMR2-DSP-NEXT: # <MCOperand Reg:291>
; MMR2-DSP-NEXT: # <MCOperand Reg:322>> ; MMR2-DSP-NEXT: # <MCOperand Reg:322>>
; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #1999 MTHI_DSP ; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #2000 MTHI_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:253> ; MMR2-DSP-NEXT: # <MCOperand Reg:253>
; MMR2-DSP-NEXT: # <MCOperand Reg:321>> ; MMR2-DSP-NEXT: # <MCOperand Reg:321>>
; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #1792 MADD_DSP ; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #1793 MADD_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:26> ; MMR2-DSP-NEXT: # <MCOperand Reg:26>
; MMR2-DSP-NEXT: # <MCOperand Reg:22> ; MMR2-DSP-NEXT: # <MCOperand Reg:22>
; MMR2-DSP-NEXT: # <MCOperand Reg:23> ; MMR2-DSP-NEXT: # <MCOperand Reg:23>
; MMR2-DSP-NEXT: # <MCOperand Reg:26>> ; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #1862 MFLO_DSP ; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #1863 MFLO_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:321> ; MMR2-DSP-NEXT: # <MCOperand Reg:321>
; MMR2-DSP-NEXT: # <MCOperand Reg:26>> ; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
; MMR2-DSP-NEXT: jr $ra # <MCInst #1639 JR_MM ; MMR2-DSP-NEXT: jr $ra # <MCInst #1640 JR_MM
; MMR2-DSP-NEXT: # <MCOperand Reg:19>> ; MMR2-DSP-NEXT: # <MCOperand Reg:19>>
; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #1856 MFHI_DSP ; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #1857 MFHI_DSP
; MMR2-DSP-NEXT: # <MCOperand Reg:322> ; MMR2-DSP-NEXT: # <MCOperand Reg:322>
; MMR2-DSP-NEXT: # <MCOperand Reg:26>> ; MMR2-DSP-NEXT: # <MCOperand Reg:26>>
entry: entry:
%conv = sext i32 %a to i64 %conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64 %conv1 = sext i32 %b to i64
%mul = mul nsw i64 %conv, %conv1 %mul = mul nsw i64 %conv, %conv1
%add = add nsw i64 %mul, 1 %add = add nsw i64 %mul, 1
ret i64 %add ret i64 %add
} }