[AMDGPU] Allow MIMG with no uses in adjustWritemask in isel

[dstuttard]

Summary

If an MIMG instruction has managed to get through to adjustWritemask in isel but
has no uses (and doesn't enable TFC) then prevent an assertion by not attempting
to adjust the writemask.

The instruction will be removed anyway.

Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7

[arsenm]

test/CodeGen/AMDGPU/img-nouse-adjust.ll

14–15

The trap should be removed and the unreachable replaced with return

[dstuttard]

test/CodeGen/AMDGPU/img-nouse-adjust.ll

14–15

The problem doesn't happen if you remove the trap.

[arsenm]

test/CodeGen/AMDGPU/img-nouse-adjust.ll

14–15

A fake side effect asm call would probably work and be less likely to break for unrelated reasons

[dstuttard]

Modified test in line with review comments

[dstuttard]

test/CodeGen/AMDGPU/img-nouse-adjust.ll

14–15

Yes, that worked - thanks.

[dstuttard]

ping

[arsenm]

LGTM

lib/Target/AMDGPU/SIISelLowering.cpp

if (UsesTFC && Lane == TFCLane) {
       Users[Lane] = *I;
       NewDmask |= 1 << Comp;
     }
   }
 
   // Don't allow 0 dmask, as hardware assumes one channel enabled.
   bool NoChannels = !NewDmask;
   if (NoChannels) {
+    if (!UsesTFC) {
+      // No uses of the result and not using TFC. Then do nothing.
+      return Node;
+    }
     // If the original dmask has one channel - then nothing to do
     if (OldBitsSet == 1)
       return Node;
     // Use an arbitrary dmask - required for the instruction to work
     NewDmask = 1;
   }
   // Abort if there's no change
   if (NewDmask == OldDmask)

test/CodeGen/AMDGPU/img-nouse-adjust.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
+
+; We're really just checking for no crashes
+; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
+; In reality, it's hard to get an image intrinsic into AdjustWriteMask with no uses as it will usually get removed
+; first, but it can happen, hence the fix associated with this test
+
+; GCN-LABEL: name: _amdgpu_cs_main
+; GCN-LABEL: bb.0
+; GCN: IMAGE_LOAD_V4_V2
+define amdgpu_cs void @_amdgpu_cs_main() local_unnamed_addr #0 {
+.entry:
+  %0 = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
+  call void @llvm.trap()
+  unreachable
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
+
+; Function Attrs: cold noreturn nounwind
+declare void @llvm.trap() #2
+  
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly  }
+attributes #2 = { cold noreturn nounwind }
+attributes #3 = { nounwind }