[AArch64/ARM] Fix two compiler warnings in InstructionSelector, NFCI

[Hahnfeld]

Summary

1. GCC complains that KnownValid is set but not used.
2. In ARMInstructionSelector::selectGlobal() the code is mixing "enumeral and non-enumeral type in conditional expression". Solve this by casting to unsigned which is the final type anyway.

llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
   auto CheckCopy = [&]() {
     // If we have a bitcast or something, we can't have physical registers.
     assert(
         (I.isCopy() ||
          (!TargetRegisterInfo::isPhysicalRegister(I.getOperand(0).getReg()) &&
           !TargetRegisterInfo::isPhysicalRegister(I.getOperand(1).getReg()))) &&
         "No phys reg on generic operator!");
     assert(KnownValid || isValidCopy(I, DstRegBank, MRI, TRI, RBI));
+    (void)KnownValid;
     return true;
   };
 
   // Is this a copy? If so, then we may need to insert a subregister copy, or
   // a SUBREG_TO_REG.
   if (I.isCopy()) {
     // Yes. Check if there's anything to fix up.
     const TargetRegisterClass *SrcRC = getMinClassForRegBank(

llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp

if (TM.isPositionIndependent()) {
     // and indirect accesses, and the ones for indirect accesses include the
     // load from GOT. For Thumb mode, we use the same pseudoinstruction for both
     // direct and indirect accesses, and we need to manually generate the load
     // from GOT.
     bool UseOpcodeThatLoads = Indirect && !STI.isThumb();
 
     // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
     // support it yet. See PR28229.
-    unsigned Opc = UseMovt && !STI.isTargetELF()
-                       ? (UseOpcodeThatLoads ? ARM::MOV_ga_pcrel_ldr
-                                             : Opcodes.MOV_ga_pcrel)
-                       : (UseOpcodeThatLoads ? ARM::LDRLIT_ga_pcrel_ldr
-                                             : Opcodes.LDRLIT_ga_pcrel);
+    unsigned Opc =
+        UseMovt && !STI.isTargetELF()
+            ? (UseOpcodeThatLoads ? (unsigned)ARM::MOV_ga_pcrel_ldr
+            : (UseOpcodeThatLoads ? (unsigned)ARM::LDRLIT_ga_pcrel_ldr
     MIB->setDesc(TII.get(Opc));
 
     int TargetFlags = ARMII::MO_NO_FLAG;
     if (STI.isTargetDarwin())
       TargetFlags |= ARMII::MO_NONLAZY;
     if (STI.isGVInGOT(GV))
       TargetFlags |= ARMII::MO_GOT;
     MIB->getOperand(1).setTargetFlags(TargetFlags);