AMDGPU/GlobalISel: Implement select for 32-bit G_ADD

[arsenm]

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

1

I’ve just been generating all of the global isel test checks

4

Can you include the type in the name

40

64-bit scalar at least looks like is already handled that should have a test here

[tstellar]

Clean up test

[tstellar]

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

40

Where did you see this? I tried to add the test, but it complained that 64-bit G_ADD was not legal.

[arsenm]

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

40

bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
Creates an S_ADD_U32 + S_ADDC_U32 pair

[tstellar]

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

40

Because 64-bit G_ADD is not legal yet, this code is only ever called when selecting G_GEP.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

132 ↗

(On Diff #193643)

Should use the _e64 version

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

132 ↗

(On Diff #193643)

I tried to do this, but there are a few problems. I have a supplemental patch which uses the right version for gfx9.

lib/Target/AMDGPU/AMDGPUGISel.td

multiclass GISelVop2IntrPat <
   // generic machine instruction may be better that matching the intrinsic
   // directly.
   def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
 }
 
 def : GISelSop2Pat <or, S_OR_B32, i32>;
 def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
 
+def : GISelSop2Pat <add, S_ADD_I32, i32>;
+def : GISelVop2Pat <add, V_ADD_I32_e32, i32>;
+
 def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
 let AddedComplexity = 100 in {
 let SubtargetPredicate = isGFX6GFX7 in {
 def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
 }
 def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
 }
 def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::select(MachineInstr &I,
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCOPY(I);
     return true;
   }
 
   switch (I.getOpcode()) {
+  case TargetOpcode::G_ADD:
+    if (selectG_ADD(I))
+      return true;
+    LLVM_FALLTHROUGH;
   default:
     return selectImpl(I, CoverageInfo);
-  case TargetOpcode::G_ADD:
-    return selectG_ADD(I);
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_BITCAST:
     return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
   case TargetOpcode::G_FCONSTANT:
     return selectG_CONSTANT(I);
   case TargetOpcode::G_EXTRACT:
     return selectG_EXTRACT(I);

test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+---
+name:            add
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: add
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
+    ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+    ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:vgpr(s32) = COPY $vgpr0
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
+    %4:sgpr(s32) = G_CONSTANT i32 1
+    %5:sgpr(s32) = G_CONSTANT i32 4096
+
+    ; add ss
+    ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[SGPR0]], [[SGPR1]]
+    %6:sgpr(s32) = G_ADD %0, %1
+
+    ; add vs
+    ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[SS]], [[VGPR0]]
+    %7:vgpr(s32) = G_ADD %2, %6
+
+    ; add sv
+    ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[SS]], [[VS]]
+    %8:vgpr(s32) = G_ADD %6, %7
+
+    ; add vv
+    ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[SV]], [[VGPR0]]
+    %9:vgpr(s32) = G_ADD %8, %2
+
+    G_STORE %9, %3 :: (store 4, addrspace 1)
+
+...