[PowerPC] Set useful flags for vector imm setting instructions

[jsji]

Summary

Vector imm setting instructions like

V_SET0B/V_SET0H/V_SET0
V_SETALLONESB/V_SETALLONESH/V_SETALLONES
XXLXORz/XXLXORspz/XXLXORdpz

Should behave like LI8.
We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc.

[jsji]

Ping~

[jsji]

Ping...

[nemanjai]

LGTM. Sorry about the delay.

[jsji]

Update testcases(pr36292.ll) to reflect upstream changes.

[jsji]

No-relevant testcase update committed in NFC patch https://reviews.llvm.org/rL355945 first.
Update patch to show relevant changes only.

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 // i32 element comparisons.
 def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
 def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
 def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
 
-let isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
+    isReMaterializable = 1 in {
+
 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
                       "vxor $vD, $vD, $vD", IIC_VecFP,
                       [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
                       "vxor $vD, $vD, $vD", IIC_VecFP,
                       [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
 def V_SET0  : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
                       "vxor $vD, $vD, $vD", IIC_VecFP,

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
   case PPC::LI:
   case PPC::LI8:
   case PPC::LIS:
   case PPC::LIS8:
   case PPC::QVGPCI:
   case PPC::ADDIStocHA:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
+  case PPC::XXLXORz:
+  case PPC::XXLXORspz:
+  case PPC::XXLXORdpz:
+  case PPC::V_SET0B:
+  case PPC::V_SET0H:
+  case PPC::V_SET0:
+  case PPC::V_SETALLONESB:
+  case PPC::V_SETALLONESH:
+  case PPC::V_SETALLONES:
     return true;
   }
   return false;
 }
 
 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                           int &FrameIndex) const {
   unsigned Opcode = MI.getOpcode();

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Uses = [RM] in {
   def XXLORf: XX3Form<60, 146,
                       (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
                       "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
   def XXLXOR : XX3Form<60, 154,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
                        [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
   } // isCommutable
-  let isCodeGenOnly = 1 in
+
+  let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
+      isReMaterializable = 1 in {
     def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins),
                        "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
                        [(set v4i32:$XT, (v4i32 immAllZerosV))]>;
-
-  let isCodeGenOnly = 1 in {
     def XXLXORdpz : XX3Form_SetZero<60, 154,
                          (outs vsfrc:$XT), (ins),
                          "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
                          [(set f64:$XT, (fpimm0))]>;
     def XXLXORspz : XX3Form_SetZero<60, 154,
                          (outs vssrc:$XT), (ins),
                          "xxlxor $XT, $XT, $XT", IIC_VecGeneral,
                          [(set f32:$XT, (fpimm0))]>;

llvm/test/CodeGen/PowerPC/optimize-andiso.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
 define float @floatundisf(i64 %a) {
 ; CHECK-LABEL: floatundisf:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_2
-; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    xxlxor f1, f1, f1
-; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB0_2: # %sw.epilog
+; CHECK-NEXT:    bclr 12, 4*cr5+lt, 0
+; CHECK-NEXT:  # %bb.1: # %sw.epilog
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    li r5, 2
 ; CHECK-NEXT:    andis. r4, r3, 1024
 ; CHECK-NEXT:    li r4, 3
 ; CHECK-NEXT:    isel r4, r5, r4, eq
 ; CHECK-NEXT:    srd r3, r3, r4
 ; CHECK-NEXT:    rlwinm r3, r3, 0, 9, 31
 ; CHECK-NEXT:    mtvsrd f0, r3

llvm/test/CodeGen/PowerPC/pr36292.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s  | \
 ; RUN:   FileCheck %s --implicit-check-not=mtctr --implicit-check-not=bdnz
 $test = comdat any
 
 ; No CTR loop due to frem (since it is always a call).
 define void @test() #0 comdat {
 ; CHECK-LABEL: test:
-; CHECK:    ld 29, 0(3)
-; CHECK:    ld 30, 40(1)
-; CHECK:    xxlxor 31, 31, 31
-; CHECK:    cmpld 30, 29
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -64(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r29, -24
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    std 29, 40(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 30, 48(1) # 8-byte Folded Spill
+; CHECK-NEXT:    ld 29, 0(3)
+; CHECK-NEXT:    ld 30, 32(1)
+; CHECK-NEXT:    cmpld 30, 29
 ; CHECK-NEXT:    bge- 0, .LBB0_2
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_1: # %bounds.ok
-; CHECK:    fmr 1, 31
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1 
 ; CHECK-NEXT:    lfsx 2, 0, 3
+; CHECK-NEXT:    xxlxor 1, 1, 1
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 30, 30, 1
 ; CHECK-NEXT:    stfsx 1, 0, 3
 ; CHECK-NEXT:    cmpld 30, 29
 ; CHECK-NEXT:    blt+ 0, .LBB0_1
 ; CHECK-NEXT:  .LBB0_2: # %bounds.fail
-; CHECK-NEXT:    std 30, 40(1)
+; CHECK-NEXT:    std 30, 32(1)
   %pos = alloca i64, align 8
   br label %forcond
 
 forcond:                                          ; preds = %bounds.ok, %0
   %1 = load i64, i64* %pos
   %.len1 = load i64, i64* undef
   %bounds.cmp = icmp ult i64 %1, %.len1
   br i1 %bounds.cmp, label %bounds.ok, label %bounds.fail

llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 @ub = external global [1024 x i32], align 4
 @uc = external global [1024 x i32], align 4
 
 ; Function Attrs: noinline nounwind
 define <4 x i32> @_Z8example9Pj(<4 x i32>* %addr1, i64 %input1, i64 %input2) #0 {
 entry:
   br label %vector.body
 
 ; CHECK-LABEL: @_Z8example9Pj
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
-; CHECK: vmr
+; CHECK: xxlxor 
+; CHECK: xxlxor 
+; CHECK: xxlxor 
+; CHECK: xxlxor 
+; CHECK: xxlxor 
 
 vector.body:                                      ; preds = %vector.body, %entry
   %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
   %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ]
   %vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ]
   %vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ]
   %vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ]
   %vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ]