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Differential D58078

GlobalISel: Implement widenScalar for g_extract scalar results
ClosedPublic

Authored by arsenm on Feb 11 2019, 2:47 PM.

Details

Reviewers
aemerson
aditya_nandakumar
paquette
volkan
dsanders

Diff Detail

Event Timeline

arsenm created this revision.Feb 11 2019, 2:47 PM
Herald added subscribers: Petar.Avramovic, kristof.beyls, rovka and 3 others. · View Herald TranscriptFeb 11 2019, 2:47 PM
aemerson accepted this revision.Feb 18 2019, 1:58 PM

LGTM.

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
474

Out of curiosity, why does this need changing?

This revision is now accepted and ready to land.Feb 18 2019, 1:58 PM
arsenm marked an inline comment as done.Feb 18 2019, 2:11 PM
arsenm added inline comments.
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
474

A random assortment of functions in MachineIRBuilder don't use SrcOp/DstOp, so this makes it consistent with the other operations. I can commit this separately

arsenm closed this revision.Feb 18 2019, 2:39 PM

r354292-354293

Revision Contents

PathSize
include/
llvm/
CodeGen/
GlobalISel/
11 lines
IR/
9 lines
lib/
CodeGen/
GlobalISel/
54 lines
27 lines
Target/
AMDGPU/
5 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
293 lines

Diff 186343

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines MachineFunction &getMF() {
return *State.MF; return *State.MF;
} }
const MachineFunction &getMF() const { const MachineFunction &getMF() const {
assert(State.MF && "MachineFunction is not set"); assert(State.MF && "MachineFunction is not set");
return *State.MF; return *State.MF;
} }
const DataLayout &getDataLayout() const {
return getMF().getFunction().getParent()->getDataLayout();
}
/// Getter for DebugLoc /// Getter for DebugLoc
const DebugLoc &getDL() { return State.DL; } const DebugLoc &getDL() { return State.DL; }
/// Getter for MRI /// Getter for MRI
MachineRegisterInfo *getMRI() { return State.MRI; } MachineRegisterInfo *getMRI() { return State.MRI; }
const MachineRegisterInfo *getMRI() const { return State.MRI; } const MachineRegisterInfo *getMRI() const { return State.MRI; }
/// Getter for the State /// Getter for the State
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Linespublic:
/// \pre setBasicBlock or setMI must have been called. /// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res must be a generic virtual register with scalar or vector type. /// \pre \p Res must be a generic virtual register with scalar or vector type.
/// \pre \p Op must be a generic virtual register with scalar or vector type. /// \pre \p Op must be a generic virtual register with scalar or vector type.
/// \pre \p Op must be smaller than \p Res /// \pre \p Op must be smaller than \p Res
/// ///
/// \return The newly created instruction. /// \return The newly created instruction.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op); MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
/// Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
}
/// \return The opcode of the extension the target wants to use for boolean /// \return The opcode of the extension the target wants to use for boolean
/// values. /// values.
unsigned getBoolExtOp(bool IsVec, bool IsFP) const; unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
// Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
// = G_ZEXT \p Op depending on how the target wants to extend boolean values. // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
bool IsFP); bool IsFP);
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
MachineMemOperand &MMO); MachineMemOperand &MMO);
/// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`. /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
/// ///
/// \pre setBasicBlock or setMI must have been called. /// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res and \p Src must be generic virtual registers. /// \pre \p Res and \p Src must be generic virtual registers.
/// ///
/// \return a MachineInstrBuilder for the newly created instruction. /// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildExtract(unsigned Res, unsigned Src, uint64_t Index); MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
/// Build and insert \p Res = IMPLICIT_DEF. /// Build and insert \p Res = IMPLICIT_DEF.
MachineInstrBuilder buildUndef(const DstOp &Res); MachineInstrBuilder buildUndef(const DstOp &Res);
/// Build and insert instructions to put \p Ops together at the specified p /// Build and insert instructions to put \p Ops together at the specified p
/// Indices to form a larger register. /// Indices to form a larger register.
/// ///
/// If the types of the input registers are uniform and cover the entirity of /// If the types of the input registers are uniform and cover the entirity of
▲ Show 20 Lines • Show All 550 Lines • Show Last 20 Lines

include/llvm/IR/DataLayout.h

Show First 20 Lines • Show All 339 Lines • ▼ Show 20 Linespublic:
unsigned getIndexSize(unsigned AS) const; unsigned getIndexSize(unsigned AS) const;
/// Return the address spaces containing non-integral pointers. Pointers in /// Return the address spaces containing non-integral pointers. Pointers in
/// this address space don't have a well-defined bitwise representation. /// this address space don't have a well-defined bitwise representation.
ArrayRef<unsigned> getNonIntegralAddressSpaces() const { ArrayRef<unsigned> getNonIntegralAddressSpaces() const {
return NonIntegralAddressSpaces; return NonIntegralAddressSpaces;
} }
bool isNonIntegralPointerType(PointerType *PT) const { bool isNonIntegralAddressSpace(unsigned AddrSpace) const {
ArrayRef<unsigned> NonIntegralSpaces = getNonIntegralAddressSpaces(); ArrayRef<unsigned> NonIntegralSpaces = getNonIntegralAddressSpaces();
return find(NonIntegralSpaces, PT->getAddressSpace()) != return find(NonIntegralSpaces, AddrSpace) != NonIntegralSpaces.end();
NonIntegralSpaces.end(); }
bool isNonIntegralPointerType(PointerType *PT) const {
return isNonIntegralAddressSpace(PT->getAddressSpace());
} }
bool isNonIntegralPointerType(Type *Ty) const { bool isNonIntegralPointerType(Type *Ty) const {
auto *PTy = dyn_cast<PointerType>(Ty); auto *PTy = dyn_cast<PointerType>(Ty);
return PTy && isNonIntegralPointerType(PTy); return PTy && isNonIntegralPointerType(PTy);
} }
/// Layout pointer size, in bits /// Layout pointer size, in bits
▲ Show 20 Lines • Show All 250 Lines • Show Last 20 Lines

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 840 Lines • ▼ Show 20 LinesLegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy) { LLT WideTy) {
if (TypeIdx != 1) unsigned DstReg = MI.getOperand(0).getReg();
return UnableToLegalize;
unsigned SrcReg = MI.getOperand(1).getReg(); unsigned SrcReg = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
LLT DstTy = MRI.getType(DstReg);
unsigned Offset = MI.getOperand(2).getImm();
if (TypeIdx == 0) {
if (SrcTy.isVector() || DstTy.isVector())
return UnableToLegalize;
SrcOp Src(SrcReg);
if (SrcTy.isPointer()) {
// Extracts from pointers can be handled only if they are really just
// simple integers.
const DataLayout &DL = MIRBuilder.getDataLayout();
if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
return UnableToLegalize;
LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
SrcTy = SrcAsIntTy;
}
if (DstTy.isPointer())
return UnableToLegalize;
if (Offset == 0) {
// Avoid a shift in the degenerate case.
MIRBuilder.buildTrunc(DstReg,
MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
MI.eraseFromParent();
return Legalized;
}
// Do a shift in the source type.
LLT ShiftTy = SrcTy;
if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
Src = MIRBuilder.buildAnyExt(WideTy, Src);
ShiftTy = WideTy;
} else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
return UnableToLegalize;
auto LShr = MIRBuilder.buildLShr(
ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
MIRBuilder.buildTrunc(DstReg, LShr);
MI.eraseFromParent();
return Legalized;
}
if (!SrcTy.isVector()) if (!SrcTy.isVector())
return UnableToLegalize; return UnableToLegalize;
unsigned DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
if (DstTy != SrcTy.getElementType()) if (DstTy != SrcTy.getElementType())
return UnableToLegalize; return UnableToLegalize;
unsigned Offset = MI.getOperand(2).getImm();
if (Offset % SrcTy.getScalarSizeInBits() != 0) if (Offset % SrcTy.getScalarSizeInBits() != 0)
return UnableToLegalize; return UnableToLegalize;
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
Offset); Offset);
▲ Show 20 Lines • Show All 1,792 Lines • Show Last 20 Lines

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Show First 20 Lines • Show All 446 Lines • ▼ Show 20 LinesMachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
else { else {
assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet"); assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
Opcode = TargetOpcode::G_BITCAST; Opcode = TargetOpcode::G_BITCAST;
} }
return buildInstr(Opcode, Dst, Src); return buildInstr(Opcode, Dst, Src);
} }
MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src, MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
const SrcOp &Src,
uint64_t Index) { uint64_t Index) {
LLT SrcTy = Src.getLLTTy(*getMRI());
LLT DstTy = Dst.getLLTTy(*getMRI());
#ifndef NDEBUG #ifndef NDEBUG
assert(getMRI()->getType(Src).isValid() && "invalid operand type"); assert(SrcTy.isValid() && "invalid operand type");
assert(getMRI()->getType(Res).isValid() && "invalid operand type"); assert(DstTy.isValid() && "invalid operand type");
assert(Index + getMRI()->getType(Res).getSizeInBits() <= assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
getMRI()->getType(Src).getSizeInBits() &&
"extracting off end of register"); "extracting off end of register");
#endif #endif
if (getMRI()->getType(Res).getSizeInBits() == if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
getMRI()->getType(Src).getSizeInBits()) {
assert(Index == 0 && "insertion past the end of a register"); assert(Index == 0 && "insertion past the end of a register");
return buildCast(Res, Src); return buildCast(Dst, Src);
} }
return buildInstr(TargetOpcode::G_EXTRACT) auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
.addDef(Res) Dst.addDefToMIB(*getMRI(), Extract);
aemersonUnsubmitted
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ReplyInline Actions

Out of curiosity, why does this need changing?

aemerson: Out of curiosity, why does this need changing?
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

A random assortment of functions in MachineIRBuilder don't use SrcOp/DstOp, so this makes it consistent with the other operations. I can commit this separately

arsenm: A random assortment of functions in MachineIRBuilder don't use SrcOp/DstOp, so this makes it…
.addUse(Src) Src.addSrcToMIB(Extract);
.addImm(Index); Extract.addImm(Index);
return Extract;
} }
void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
ArrayRef<uint64_t> Indices) { ArrayRef<uint64_t> Indices) {
#ifndef NDEBUG #ifndef NDEBUG
assert(Ops.size() == Indices.size() && "incompatible args"); assert(Ops.size() == Indices.size() && "incompatible args");
assert(!Ops.empty() && "invalid trivial sequence"); assert(!Ops.empty() && "invalid trivial sequence");
assert(std::is_sorted(Indices.begin(), Indices.end()) && assert(std::is_sorted(Indices.begin(), Indices.end()) &&
▲ Show 20 Lines • Show All 585 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 510 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
const LLT &Ty0 = Query.Types[0]; const LLT &Ty0 = Query.Types[0];
const LLT &Ty1 = Query.Types[1]; const LLT &Ty1 = Query.Types[1];
return (Ty0.getSizeInBits() % 16 == 0) && return (Ty0.getSizeInBits() % 16 == 0) &&
(Ty1.getSizeInBits() % 16 == 0); (Ty1.getSizeInBits() % 16 == 0);
}) })
.widenScalarIf( .widenScalarIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
const LLT Ty1 = Query.Types[1]; const LLT Ty1 = Query.Types[1];
return (Ty1.getScalarSizeInBits() < 16); return Ty1.isVector() && Ty1.getScalarSizeInBits() < 16;
}, },
LegalizeMutations::widenScalarOrEltToNextPow2(1, 16)); LegalizeMutations::widenScalarOrEltToNextPow2(1, 16))
.clampScalar(0, S16, S256);
// TODO: vectors of pointers // TODO: vectors of pointers
getActionDefinitionsBuilder(G_BUILD_VECTOR) getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalForCartesianProduct(AllS32Vectors, {S32}) .legalForCartesianProduct(AllS32Vectors, {S32})
.legalForCartesianProduct(AllS64Vectors, {S64}) .legalForCartesianProduct(AllS64Vectors, {S64})
.clampNumElements(0, V16S32, V16S32) .clampNumElements(0, V16S32, V16S32)
.clampNumElements(0, V2S64, V8S64) .clampNumElements(0, V2S64, V8S64)
.minScalarSameAs(1, 0) .minScalarSameAs(1, 0)
▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<6 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>) ; CHECK: [[TRUNC:%[0-9]+]]:_(<6 x s16>) = G_TRUNC [[DEF]](<6 x s32>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 32 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[TRUNC]](<6 x s16>), 32
; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[EXTRACT]](<2 x s16>)
%0:_(<6 x s16>) = G_IMPLICIT_DEF %0:_(<6 x s16>) = G_IMPLICIT_DEF
%1:_(<2 x s16>) = G_EXTRACT %0, 32 %1:_(<2 x s16>) = G_EXTRACT %0, 32
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
---
name: test_extract_s8_s16_offset0
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 0
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_extract_s8_s16_offset1
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_extract_s8_s16_offset8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 8
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_extract_s8_s32_offset0
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_s32_offset1
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_s32_offset8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_s32_offset16
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_s32_offset24
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_p3_offset0
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_p3_offset0
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_p3_offset8
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_p3_offset8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s1_s8_offset0
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s1_s8_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1) = G_EXTRACT %1, 0
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_extract_s1_s8_offset2
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s1_s8_offset2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1) = G_EXTRACT %1, 2
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: test_extract_s8_s64_offset2
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s8_s64_offset2
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s8) = G_EXTRACT %0, 2
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s8_s64_offset16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s8_s64_offset16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s16_s64_offset16
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s16_s64_offset16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 16
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s16_s64_offset32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s16_s64_offset32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 32
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...
---
name: test_extract_s16_s64_offset48
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s16_s64_offset48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY]](s64), 48
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_EXTRACT %0, 48
%2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2
...