[AArch64] Print instruction before atomic semantic annotations

[DavidSpickett]

Summary

Commit r353303 added annotations when acquire semantics
were dropped from an instruction.

printAnnotation was called before printInstruction.
So if you didn't set a separate comment output stream
you got <comment><instr> instead of <instr><comment>
as expected.

To fix this move the new printAnnotation to after
the instruction is printed.

[olista01]

I think it would be neater to move this annotation printing code to after the regular printAliasInstr/printInstruction calls at the end of the function (line 300). As it is, this patch will drop any other annotations on the instruction, because it doesn't call printAnnotation(O, Annot).

[DavidSpickett]

In D58059#1396146, @olista01 wrote:

I think it would be neater to move this annotation printing code to after the regular printAliasInstr/printInstruction calls at the end of the function (line 300). As it is, this patch will drop any other annotations on the instruction, because it doesn't call printAnnotation(O, Annot).

Done.

[olista01]

LGTM

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
   unsigned Opcode = MI->getOpcode();
 
   if (Opcode == AArch64::SYSxt)
     if (printSysAlias(MI, STI, O)) {
       printAnnotation(O, Annot);
       return;
     }
 
-  if (atomicBarrierDroppedOnZero(Opcode) &&
-      (MI->getOperand(0).getReg() == AArch64::XZR ||
-       MI->getOperand(0).getReg() == AArch64::WZR))
-    printAnnotation(O, "acquire semantics dropped since destination is zero");
-
   // SBFM/UBFM should print to a nicer aliased form if possible.
   if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
       Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
     const MCOperand &Op0 = MI->getOperand(0);
     const MCOperand &Op1 = MI->getOperand(1);
     const MCOperand &Op2 = MI->getOperand(2);
     const MCOperand &Op3 = MI->getOperand(3);
 
if (Opcode == AArch64::TSB) {
     O << "\ttsb\tcsync";
     return;
   }
 
   if (!printAliasInstr(MI, STI, O))
     printInstruction(MI, STI, O);
 
   printAnnotation(O, Annot);
+
+  if (atomicBarrierDroppedOnZero(Opcode) &&
+      (MI->getOperand(0).getReg() == AArch64::XZR ||
+       MI->getOperand(0).getReg() == AArch64::WZR)) {
+    printAnnotation(O, "acquire semantics dropped since destination is zero");
+  }
 }
 
 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
                                 bool &IsTbx) {
   switch (Opcode) {
   case AArch64::TBXv8i8One:
   case AArch64::TBXv8i8Two:
   case AArch64::TBXv8i8Three: