[mips][microMIPS] Implement CodeGen support for ADDIUR2 instruction

[jkolek]

Summary

Implement CodeGen support for 16-bit microMIPS ADDIUR2 instruction.

[sstankovic]

LGTM

[jkolek]

Closed by commit rL222352 (authored by @jkolek).

lib/Target/Mips/MicroMipsInstrInfo.td

 def uimm4_andi : Operand<i32> {
   let EncoderMethod = "getUImm4AndValue";
 }
 
 def simm3_lsa2 : Operand<i32> {
   let EncoderMethod = "getSImm3Lsa2Value";
 }
 
+def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
+                                           ((Imm % 4 == 0) &&
+                                            Imm < 28 && Imm > 0);}]>;
+
 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
 
 def immZExtAndi16 : ImmLeaf<i32,
   [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
             Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
             Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
 
 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
   def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
 }
 
 //===----------------------------------------------------------------------===//
 // MicroMips arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
+def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
+              (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
               (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
               (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
 
 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
               (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
 def : MipsPat<(and GPR32:$src, immZExt16:$imm),

test/CodeGen/Mips/micromips-addiu.ll

 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4
+@z = global i32 60929, align 4
 @.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
 
 define i32 @main() nounwind {
 entry:
   %0 = load i32* @x, align 4
   %addiu1 = add i32 %0, -7
   %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
                                   ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu1)
 
   %1 = load i32* @y, align 4
   %addiu2 = add i32 %1, 55
   %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
                                   ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
+
+  %2 = load i32* @z, align 4
+  %addiu3 = add i32 %2, 24
+  %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
+                                  ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu3)
   ret i32 0
 }
 
 declare i32 @printf(i8*, ...)
 
 ; CHECK: addius5  ${{[0-9]+}}, -7
 ; CHECK: addiu    ${{[0-9]+}}, ${{[0-9]+}}, 55
+; CHECK: addiur2  ${{[0-9]+}}, ${{[0-9]+}}, 24