[AMDGPU][MC] Added support of lds_direct operand

[dp]

Summary

See bug 39293: https://bugs.llvm.org/show_bug.cgi?id=39293

Known issues:

• This is a simple implementation assuming that lds_direct support is not needed in codegen. The implementation will have to be completely rewritten in case lds_direct support is required in the future. This is because, for example, m0 has to be added to USES for instructions accessing lds_direct.
• Not clear if lds_direct should be disabled for SDWA. AMD documentation is silent about SDWA but SP3 seems to disable it.
• AMD documentation explicitly states which opcodes do not support lds_direct. However looks like that the list is incomplete as SP3 disables lds_direct for most 'rev' opcodes.
• The enumeration of opcodes which do not support lds_direct is already long enough and may need to be expanded further. I was thinking about adding a TS flag to label the corresponding opcodes. However there are not many free bits left in TSFlags and I was reluctant to use a bit for this purpose.

What is missing:

• This patch does not enable lds_direct for v_readfirstlane_b32, v_readlane_b32 and v_writelane_b32. This will be implemented by a separate patch.
• Assembler documentation should be updated with a description of lds_support. This will be added by a separate patch.

[artem.tamazov]

Looks good from assember's side.

[rampitec]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

for (const MachineInstr &MI : MBB) {
         case AMDGPU::FLAT_SCR_HI:
           continue;
 
         case AMDGPU::XNACK_MASK:
         case AMDGPU::XNACK_MASK_LO:
         case AMDGPU::XNACK_MASK_HI:
           llvm_unreachable("xnack_mask registers should not be used");
 
+        case AMDGPU::LDS_DIRECT:
+          llvm_unreachable("lds_direct register should not be used");
+
         case AMDGPU::TBA:
         case AMDGPU::TBA_LO:
         case AMDGPU::TBA_HI:
         case AMDGPU::TMA:
         case AMDGPU::TMA_LO:
         case AMDGPU::TMA_HI:
           llvm_unreachable("trap handler registers should not be used");
 

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateSOPLiteral(const MCInst &Inst) const;
   bool validateConstantBusLimitations(const MCInst &Inst);
   bool validateEarlyClobberLimitations(const MCInst &Inst);
   bool validateIntClampSupported(const MCInst &Inst);
   bool validateMIMGAtomicDMask(const MCInst &Inst);
   bool validateMIMGGatherDMask(const MCInst &Inst);
   bool validateMIMGDataSize(const MCInst &Inst);
   bool validateMIMGD16(const MCInst &Inst);
+  bool validateLdsDirect(const MCInst &Inst);
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
   bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
   unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
 
   bool trySkipId(const StringRef Id);
   bool trySkipToken(const AsmToken::TokenKind Kind);
   bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
   bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");

 }
 
 static unsigned getSpecialRegForName(StringRef RegName) {
   return StringSwitch<unsigned>(RegName)
     .Case("exec", AMDGPU::EXEC)
     .Case("vcc", AMDGPU::VCC)
     .Case("flat_scratch", AMDGPU::FLAT_SCR)
     .Case("xnack_mask", AMDGPU::XNACK_MASK)
+    .Case("lds_direct", AMDGPU::LDS_DIRECT)
+    .Case("src_lds_direct", AMDGPU::LDS_DIRECT)
     .Case("m0", AMDGPU::M0)
     .Case("scc", AMDGPU::SCC)
     .Case("tba", AMDGPU::TBA)
     .Case("tma", AMDGPU::TMA)
     .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
     .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
     .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)
     .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)
bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
   if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {
     if (isCI() || isSI())
       return false;
   }
 
   return true;
 }
 
+bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
+
+  using namespace SIInstrFlags;
+  const unsigned Opcode = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opcode);
+
+  // lds_direct register is defined so that it can be used
+  // with 9-bit operands only. Ignore encodings which do not accept these.
+  if ((Desc.TSFlags & (VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA)) == 0)
+    return true;
+
+  const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
+  const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
+  const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
+
+  const int SrcIndices[] = { Src1Idx, Src2Idx };
+
+  // lds_direct cannot be specified as either src1 or src2.
+  for (int SrcIdx : SrcIndices) {
+    if (SrcIdx == -1) break;
+    const MCOperand &Src = Inst.getOperand(SrcIdx);
+    if (Src.isReg() && Src.getReg() == LDS_DIRECT) {
+      return false;
+    }
+  }
+
+  if (Src0Idx == -1)
+    return true;
+
+  const MCOperand &Src = Inst.getOperand(Src0Idx);
+  if (!Src.isReg() || Src.getReg() != LDS_DIRECT)
+    return true;
+
+  // lds_direct is specified as src0. Check additional limitations.
+
+  // FIXME: This is a workaround for bug 37943
+  // which allows 64-bit VOP3 opcodes use 32-bit operands.
+  if (AMDGPU::getRegOperandSize(getMRI(), Desc, Src0Idx) != 4)
+    return false;
+
+  // Documentation does not disable lds_direct for SDWA, but SP3 assembler does.
+  // FIXME: This inconsistence needs to be investigated further.
+  if (Desc.TSFlags & SIInstrFlags::SDWA)
+    return false;
+
+  // The following opcodes do not accept lds_direct which is explicitly stated
+  // in AMD documentation. However SP3 disables lds_direct for most other 'rev'
+  // opcodes as well (e.g. for v_subrev_u32 but not for v_subrev_f32).
+  // FIXME: This inconsistence needs to be investigated further.
+  switch (Opcode) {
+  case AMDGPU::V_LSHLREV_B32_e32_si:
+  case AMDGPU::V_LSHLREV_B32_e64_si:
+  case AMDGPU::V_LSHLREV_B16_e32_vi:
+  case AMDGPU::V_LSHLREV_B16_e64_vi:
+  case AMDGPU::V_LSHLREV_B32_e32_vi:
+  case AMDGPU::V_LSHLREV_B32_e64_vi:
+  case AMDGPU::V_LSHLREV_B64_vi:
+  case AMDGPU::V_LSHRREV_B32_e32_si:
+  case AMDGPU::V_LSHRREV_B32_e64_si:
+  case AMDGPU::V_LSHRREV_B16_e32_vi:
+  case AMDGPU::V_LSHRREV_B16_e64_vi:
+  case AMDGPU::V_LSHRREV_B32_e32_vi:
+  case AMDGPU::V_LSHRREV_B32_e64_vi:
+  case AMDGPU::V_LSHRREV_B64_vi:
+  case AMDGPU::V_ASHRREV_I32_e64_si:
+  case AMDGPU::V_ASHRREV_I32_e32_si:
+  case AMDGPU::V_ASHRREV_I16_e32_vi:
+  case AMDGPU::V_ASHRREV_I16_e64_vi:
+  case AMDGPU::V_ASHRREV_I32_e32_vi:
+  case AMDGPU::V_ASHRREV_I32_e64_vi:
+  case AMDGPU::V_ASHRREV_I64_vi:
+  case AMDGPU::V_PK_LSHLREV_B16_vi:
+  case AMDGPU::V_PK_LSHRREV_B16_vi:
+  case AMDGPU::V_PK_ASHRREV_I16_vi:
+    return false;
+  default:
+    return true;
+  }
+}
+
 bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
   unsigned Opcode = Inst.getOpcode();
   const MCInstrDesc &Desc = MII.get(Opcode);
   if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC)))
     return true;
 
   const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
for (int OpIdx : OpIndices) {
     }
   }
 
   return NumLiterals <= 1;
 }
 
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
                                           const SMLoc &IDLoc) {
+  if (!validateLdsDirect(Inst)) {
+    Error(IDLoc,
+      "invalid use of lds_direct");
+    return false;
+  }
   if (!validateSOPLiteral(Inst)) {
     Error(IDLoc,
       "only one literal operand is allowed");
     return false;
   }
   if (!validateConstantBusLimitations(Inst)) {
     Error(IDLoc,
       "invalid operand (violates constant bus restrictions)");

llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
   case 237: return createRegOperand(SRC_PRIVATE_BASE);
   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
     // TODO: SRC_POPS_EXITING_WAVE_ID
     // ToDo: no support for vccz register
   case 251: break;
     // ToDo: no support for execz register
   case 252: break;
   case 253: return createRegOperand(SCC);
+  case 254: return createRegOperand(LDS_DIRECT);
   default: break;
   }
   return errOperand(Val, "unknown operand encoding " + Twine(Val));
 }
 
 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
   using namespace AMDGPU;
 

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

case AMDGPU::M0:
     O << "m0";
     return;
   case AMDGPU::FLAT_SCR:
     O << "flat_scratch";
     return;
   case AMDGPU::XNACK_MASK:
     O << "xnack_mask";
     return;
+  case AMDGPU::LDS_DIRECT:
+    O << "src_lds_direct";
+    return;
   case AMDGPU::VCC_LO:
     O << "vcc_lo";
     return;
   case AMDGPU::VCC_HI:
     O << "vcc_hi";
     return;
   case AMDGPU::TBA_LO:
     O << "tba_lo";

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
   reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
   reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE);
   reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
 
   // Reserve xnack_mask registers - support is not implemented in Codegen.
   reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK);
 
+  // Reserve lds_direct register - support is not implemented in Codegen.
+  reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT);
+
   // Reserve Trap Handler registers - support is not implemented in Codegen.
   reserveRegisterTuples(Reserved, AMDGPU::TBA);
   reserveRegisterTuples(Reserved, AMDGPU::TMA);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
   reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td

 def SCC : SIReg<"scc", 253>;
 def M0 : SIReg <"m0", 124>;
 
 def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>;
 def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
 def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
 def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
 
+def LDS_DIRECT : SIReg <"lds_direct", 254>;
+
 def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
 def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
 
 def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>,
                  DwarfRegAlias<XNACK_MASK_LO> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = 104;

 }
 
 def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
   (add PRIVATE_RSRC_REG)> {
   let isAllocatable = 0;
   let CopyCost = -1;
 }
 
+def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
+  (add LDS_DIRECT)> {
+  let isAllocatable = 0;
+  let CopyCost = -1;
+}
+
 // Subset of SReg_32 without M0 for SMRD instructions and alike.
 // See comments in SIInstructions.td for more info.
 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
   (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
    TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
    SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
   let AllocationPriority = 7;
 }
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
   let AllocationPriority = 6;
 }
 
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
   let Size = 32;
 }
 
 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
-                          (add VGPR_32, SReg_32)> {
+                          (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> {
   let isAllocatable = 0;
 }
 
 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
   let isAllocatable = 0;
 }
 
 //===----------------------------------------------------------------------===//

llvm/trunk/test/MC/AMDGPU/lds_direct-err.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9
+
+//---------------------------------------------------------------------------//
+// lds_direct may be used only with vector ALU instructions
+//---------------------------------------------------------------------------//
+
+s_and_b32 s2, lds_direct, s1
+// NOGFX9: error
+
+//---------------------------------------------------------------------------//
+// lds_direct may not be used with V_{LSHL,LSHR,ASHL}REV opcodes
+//---------------------------------------------------------------------------//
+
+v_ashrrev_i16 v0, lds_direct, v0
+// NOGFX9: error
+
+v_ashrrev_i32 v0, lds_direct, v0
+// NOGFX9: error
+
+v_lshlrev_b16 v0, lds_direct, v0
+// NOGFX9: error
+
+v_lshlrev_b32 v0, lds_direct, v0
+// NOGFX9: error
+
+v_lshrrev_b16 v0, lds_direct, v0
+// NOGFX9: error
+
+v_lshrrev_b32 v0, lds_direct, v0
+// NOGFX9: error
+
+v_pk_ashrrev_i16 v0, lds_direct, v0
+// NOGFX9: error
+
+v_pk_lshlrev_b16 v0, lds_direct, v0
+// NOGFX9: error
+
+v_pk_lshrrev_b16 v0, lds_direct, v0
+// NOGFX9: error
+
+//---------------------------------------------------------------------------//
+// lds_direct cannot be used with 64-bit and larger operands
+//---------------------------------------------------------------------------//
+
+v_add_f64 v[0:1], lds_direct, v[0:1]
+// NOGFX9: error
+
+//---------------------------------------------------------------------------//
+// Only SRC0 may specify lds_direct
+//---------------------------------------------------------------------------//
+
+v_add_i32 v0, v0, lds_direct
+// NOGFX9: error
+
+v_add_i32 lds_direct, v0, v0
+// NOGFX9: error
+
+v_fma_f32 v0, v0, v0, lds_direct
+// NOGFX9: error

llvm/trunk/test/MC/AMDGPU/lds_direct.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+
+//---------------------------------------------------------------------------//
+// VOP1/3
+//---------------------------------------------------------------------------//
+
+v_mov_b32 v0, src_lds_direct
+// GFX9: v_mov_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x02,0x00,0x7e]
+
+v_mov_b32_e64 v0, src_lds_direct
+// GFX9: v_mov_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_i32 v[0:1], src_lds_direct
+// GFX9: v_cvt_f64_i32_e32 v[0:1], src_lds_direct ; encoding: [0xfe,0x08,0x00,0x7e]
+
+v_cvt_f64_i32_e64 v[0:1], src_lds_direct
+// GFX9: v_cvt_f64_i32_e64 v[0:1], src_lds_direct ; encoding: [0x00,0x00,0x44,0xd1,0xfe,0x00,0x00,0x00]
+
+v_mov_fed_b32 v0, src_lds_direct
+// GFX9: v_mov_fed_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x12,0x00,0x7e]
+
+v_mov_fed_b32_e64 v0, src_lds_direct
+// GFX9: v_mov_fed_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x49,0xd1,0xfe,0x00,0x00,0x00]
+
+v_fract_f32 v0, src_lds_direct
+// GFX9: v_fract_f32_e32 v0, src_lds_direct ; encoding: [0xfe,0x36,0x00,0x7e]
+
+v_fract_f32_e64 v0, src_lds_direct
+// GFX9: v_fract_f32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x5b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_u16 v0, src_lds_direct
+// GFX9: v_cvt_f16_u16_e32 v0, src_lds_direct ; encoding: [0xfe,0x72,0x00,0x7e]
+
+//---------------------------------------------------------------------------//
+// VOP2/3
+//---------------------------------------------------------------------------//
+
+v_cndmask_b32 v0, src_lds_direct, v0, vcc
+// GFX9: v_cndmask_b32_e32 v0, src_lds_direct, v0, vcc ; encoding: [0xfe,0x00,0x00,0x00]
+
+v_cndmask_b32_e64 v0, src_lds_direct, v0, s[0:1]
+// GFX9: v_cndmask_b32_e64 v0, src_lds_direct, v0, s[0:1] ; encoding: [0x00,0x00,0x00,0xd1,0xfe,0x00,0x02,0x00]
+
+v_add_f32 v0, src_lds_direct, v0
+// GFX9: v_add_f32_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x02]
+
+v_add_f32_e64 v0, src_lds_direct, v0
+// GFX9: v_add_f32_e64 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x01,0xd1,0xfe,0x00,0x02,0x00]
+
+v_mul_i32_i24 v0, src_lds_direct, v0
+// GFX9: v_mul_i32_i24_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x0c]
+
+v_add_co_u32 v0, vcc, src_lds_direct, v0
+// GFX9: v_add_co_u32_e32 v0, vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x32]
+
+//---------------------------------------------------------------------------//
+// VOP3
+//---------------------------------------------------------------------------//
+
+v_add_co_u32_e64 v0, s[0:1], src_lds_direct, v0
+// GFX9: v_add_co_u32_e64 v0, s[0:1], src_lds_direct, v0 ; encoding: [0x00,0x00,0x19,0xd1,0xfe,0x00,0x02,0x00]
+
+v_madmk_f16 v0, src_lds_direct, 0x1121, v0
+// GFX9: v_madmk_f16 v0, src_lds_direct, 0x1121, v0 ; encoding: [0xfe,0x00,0x00,0x48,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v0, src_lds_direct, v0, 0x1121
+// GFX9: v_madak_f16 v0, src_lds_direct, v0, 0x1121 ; encoding: [0xfe,0x00,0x00,0x4a,0x21,0x11,0x00,0x00]
+
+v_mad_f32 v0, src_lds_direct, v0, v0
+// GFX9: v_mad_f32 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xc1,0xd1,0xfe,0x00,0x02,0x04]
+
+v_fma_f32 v0, src_lds_direct, v0, v0
+// GFX9: v_fma_f32 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xcb,0xd1,0xfe,0x00,0x02,0x04]
+
+v_min3_i16 v0, src_lds_direct, v0, v0
+// GFX9: v_min3_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xf5,0xd1,0xfe,0x00,0x02,0x04]
+
+v_max3_f16 v0, src_lds_direct, v0, v0
+// GFX9: v_max3_f16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xf7,0xd1,0xfe,0x00,0x02,0x04]
+
+//---------------------------------------------------------------------------//
+// VOP3P
+//---------------------------------------------------------------------------//
+
+v_pk_mad_i16 v0, src_lds_direct, v0, v0
+// GFX9: v_pk_mad_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c]
+
+v_pk_add_i16 v0, src_lds_direct, v0
+// GFX9: v_pk_add_i16 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x82,0xd3,0xfe,0x00,0x02,0x18]
+
+//---------------------------------------------------------------------------//
+// VOPC
+//---------------------------------------------------------------------------//
+
+v_cmp_lt_f16 vcc, src_lds_direct, v0
+// GFX9: v_cmp_lt_f16_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x42,0x7c]
+
+v_cmp_eq_f32 vcc, src_lds_direct, v0
+// GFX9: v_cmp_eq_f32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x84,0x7c]
+
+v_cmpx_neq_f32 vcc, src_lds_direct, v0
+// GFX9: v_cmpx_neq_f32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0xba,0x7c]
+
+//---------------------------------------------------------------------------//
+// lds_direct alias
+//---------------------------------------------------------------------------//
+
+v_cmp_lt_f16 vcc, lds_direct, v0
+// GFX9: v_cmp_lt_f16_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x42,0x7c]
+
+//---------------------------------------------------------------------------//
+// FIXME: enable lds_direct for the following opcodes and add tests
+//---------------------------------------------------------------------------//
+
+//v_readfirstlane_b32 s0, src_lds_direct
+//v_readlane_b32 s0, src_lds_direct, s0

llvm/trunk/test/MC/Disassembler/AMDGPU/lds_direct_gfx9.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s --check-prefix=GFX9
+
+# GFX9: v_mov_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x02,0x00,0x7e]
+0xfe,0x02,0x00,0x7e
+
+# GFX9: v_mov_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
+0x00,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00
+
+# GFX9: v_add_f32_e32 v0, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x00,0x02]
+0xfe,0x00,0x00,0x02
+
+# GFX9: v_pk_mad_i16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c]
+0x00,0x40,0x80,0xd3,0xfe,0x00,0x02,0x1c
+
+# GFX9: v_pk_mul_lo_u16 v0, src_lds_direct, v0 ; encoding: [0x00,0x00,0x81,0xd3,0xfe,0x00,0x02,0x18]
+0x00,0x00,0x81,0xd3,0xfe,0x00,0x02,0x18
+
+# GFX9: v_cmpx_le_i32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0xa6,0x7d]
+0xfe,0x00,0xa6,0x7d