[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

[dmgreen]

Summary

Noticed when codegen prepare started adding more llvm.uadd.with.overflow's, this follows
the same code path as Thumb2, removing redundant CMP's in the peephole optimiser.

[dmgreen]

lib/Target/ARM/ARMBaseInstrInfo.cpp

2923

Whoops. Forgot about this bit.

[efriedma]

lib/Target/ARM/ARMBaseInstrInfo.cpp

2624

Can you commit the reformatting separately? It's a little confusing to distinguish which changes are actually relevant.

2660

What are these "isReg" checks supposed to do? You already checked the opcode.

[dmgreen]

Fixed that bit I missed, plus better formatting and cleanup

[efriedma]

I'd like to see testcases for all the possible add/sub opcodes, if it isn't too much work.

lib/Target/ARM/ARMBaseInstrInfo.cpp

2660

The corresponding ARM/Thumb2 code checks for ADDrr; should we add the corresponding check for tADDrr?
Or does that not work for some reason?

2681

I guess it's sort of orthogonal to this patch, but this list isn't complete, if it's supposed to be a list of instructions which update the NZ bits. (Missing tADC, tSBC, tAND, tORR, tEOR, tBIC, tMVN, tASRri, tASRrr, tROR, I think.)

[dmgreen]

lib/Target/ARM/ARMBaseInstrInfo.cpp

2660

Thanks, that was lost in a reshuffle I think. It does show up some machine verifier problems with this. IsThumb1 isn't being set correctly

[dmgreen]

Updates for IsThumb1

[efriedma]

LGTM

lib/Target/ARM/ARMBaseInstrInfo.cpp

bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
   case ARM::tCMPi8:
     SrcReg = MI.getOperand(0).getReg();
     SrcReg2 = 0;
     CmpMask = ~0;
     CmpValue = MI.getOperand(1).getImm();
     return true;
   case ARM::CMPrr:
   case ARM::t2CMPrr:
+  case ARM::tCMPr:
     SrcReg = MI.getOperand(0).getReg();
     SrcReg2 = MI.getOperand(1).getReg();
     CmpMask = ~0;
     CmpValue = 0;
     return true;
   case ARM::TSTri:
   case ARM::t2TSTri:
     SrcReg = MI.getOperand(0).getReg();

 /// purpose is to update flags, can be made redundant.
 /// CMPrr can be made redundant by SUBrr if the operands are the same.
 /// CMPri can be made redundant by SUBri if the operands are the same.
 /// CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X).
 /// This function can be extended later on.
 inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
                                         unsigned SrcReg, unsigned SrcReg2,
                                         int ImmValue, const MachineInstr *OI) {
-  if ((CmpI->getOpcode() == ARM::CMPrr ||
-       CmpI->getOpcode() == ARM::t2CMPrr) &&
-      (OI->getOpcode() == ARM::SUBrr ||
-       OI->getOpcode() == ARM::t2SUBrr) &&
+  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
+      (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
       ((OI->getOperand(1).getReg() == SrcReg &&
         OI->getOperand(2).getReg() == SrcReg2) ||
        (OI->getOperand(1).getReg() == SrcReg2 &&
         OI->getOperand(2).getReg() == SrcReg)))
     return true;
 
-  if ((CmpI->getOpcode() == ARM::CMPri ||
-       CmpI->getOpcode() == ARM::t2CMPri) &&
-      (OI->getOpcode() == ARM::SUBri ||
-       OI->getOpcode() == ARM::t2SUBri) &&
+  if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
+      ((OI->getOperand(2).getReg() == SrcReg &&
+        OI->getOperand(3).getReg() == SrcReg2) ||
+       (OI->getOperand(2).getReg() == SrcReg2 &&
+        OI->getOperand(3).getReg() == SrcReg)))
+    return true;
+
+  if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
+      (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
       OI->getOperand(1).getReg() == SrcReg &&
       OI->getOperand(2).getImm() == ImmValue)
     return true;
 
+  if (CmpI->getOpcode() == ARM::tCMPi8 &&
+      (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
+      OI->getOperand(2).getReg() == SrcReg &&
+      OI->getOperand(3).getImm() == ImmValue)
+    return true;
+
   if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
       (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
        OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
       OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
       OI->getOperand(0).getReg() == SrcReg &&
       OI->getOperand(1).getReg() == SrcReg2)
     return true;
+
+  if (CmpI->getOpcode() == ARM::tCMPr &&
+      (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8) &&
+      OI->getOperand(0).isReg() && OI->getOperand(2).isReg() &&
+      OI->getOperand(0).getReg() == SrcReg &&
+      OI->getOperand(2).getReg() == SrcReg2)
+    return true;
+
   return false;
 }
 
 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
   switch (MI->getOpcode()) {
   default: return false;
   case ARM::tLSLri:
   case ARM::tLSRri:
   case ARM::tLSLrr:
   case ARM::tLSRrr:
   case ARM::tSUBrr:
   case ARM::tADDrr:
   case ARM::tADDi3:
   case ARM::tADDi8:
   case ARM::tSUBi3:
   case ARM::tSUBi8:
   case ARM::tMUL:
     IsThumb1 = true;
     LLVM_FALLTHROUGH;
   case ARM::RSBrr:
   case ARM::RSBri:
   case ARM::RSCrr:
   case ARM::RSCri:
   case ARM::ADDrr:
   case ARM::ADDri:
if (SrcReg2 != 0)
     // MI is not a candidate for CMPrr.
     MI = nullptr;
   else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
     // Conservatively refuse to convert an instruction which isn't in the same
     // BB as the comparison.
     // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
     // Thus we cannot return here.
     if (CmpInstr.getOpcode() == ARM::CMPri ||
-        CmpInstr.getOpcode() == ARM::t2CMPri)
+        CmpInstr.getOpcode() == ARM::t2CMPri ||
+        CmpInstr.getOpcode() == ARM::tCMPi8)
       MI = nullptr;
     else
       return false;
   }
 
   bool IsThumb1 = false;
   if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
     return false;
for (unsigned IO = 0, EO = Instr.getNumOperands();
         // on CMP needs to be updated to be based on SUB.
         // If we have ADD(r1, r2, X) and CMP(r1, r2), the condition code also
         // needs to be modified.
         // Push the condition code operands to OperandsToUpdate.
         // If it is safe to remove CmpInstr, the condition code of these
         // operands will be modified.
         unsigned Opc = SubAdd->getOpcode();
         bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
-                     Opc == ARM::SUBri || Opc == ARM::t2SUBri;
+                     Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
+                     Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
+                     Opc == ARM::tSUBi8;
         if (!IsSub || (SrcReg2 != 0 && SubAdd->getOperand(1).getReg() == SrcReg2 &&
                        SubAdd->getOperand(2).getReg() == SrcReg)) {
           // VSel doesn't support condition code update.
           if (IsInstrVSel)
             return false;
           // Ensure we can swap the condition.
           ARMCC::CondCodes NewCC = (IsSub ? getSwappedCondition(CC) : getCmpToAddCondition(CC));
           if (NewCC == ARMCC::AL)
             return false;

test/CodeGen/Thumb/peephole-cmp.mir

registers:
   - { id: 1, class: tgpr, preferred-register: '' }
   - { id: 2, class: tgpr, preferred-register: '' }
   - { id: 3, class: tgpr, preferred-register: '' }
 liveins:
   - { reg: '$r0', virtual-reg: '%0' }
 body:             |
   ; CHECK-LABEL: name: test1
   ; CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
-  ; CHECK-NEXT: tCMPr killed [[ADD]], [[COPY]], 14, $noreg, implicit-def $cpsr
-  ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, def $cpsr
+  ; CHECK-NEXT: tBcc %bb.2, 2, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0
 
     %0:tgpr = COPY $r0
     %1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
     tCMPr killed %1, %0, 14, $noreg, implicit-def $cpsr
     tBcc %bb.2, 3, $cpsr
registers:
   - { id: 3, class: tgpr, preferred-register: '' }
 liveins:
   - { reg: '$r0', virtual-reg: '%1' }
   - { reg: '$r1', virtual-reg: '%2' }
 body:             |
   ; CHECK-LABEL: name: test2
   ; CHECK:      [[COPY1:%[0-9]+]]:tgpr = COPY $r1
   ; CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
-  ; CHECK-NEXT: tCMPr [[COPY0]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, def $cpsr
   ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0, $r1
 
     %2:tgpr = COPY $r1
     %1:tgpr = COPY $r0
     %0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
registers:
   - { id: 1, class: tgpr, preferred-register: '' }
   - { id: 2, class: tgpr, preferred-register: '' }
   - { id: 3, class: tgpr, preferred-register: '' }
 liveins:
   - { reg: '$r0', virtual-reg: '%1' }
 body:             |
   ; CHECK-LABEL: name: test3
   ; CHECK:      [[COPY:%[0-9]+]]:tgpr = COPY $r0
-  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
-  ; CHECK-NEXT: tCMPi8 [[COPY0]], 1, 14, $noreg, implicit-def $cpsr
+  ; CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, def $cpsr
   ; CHECK-NEXT: tBcc %bb.2, 3, $cpsr
   bb.0 (%ir-block.0):
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0
 
     %1:tgpr = COPY $r0
     %0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
     tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr