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[ARM] Add some more missing T1 opcodes for the peephole optimisier
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Authored by dmgreen on Feb 15 2019, 6:35 AM.

Details

Summary

As pointed out in D57833, we can add a few extra Thumb1 opcodes
to the peephole optimisers ability to remove CMP instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

dmgreen created this revision.Feb 15 2019, 6:35 AM
efriedma accepted this revision.Feb 19 2019, 11:11 AM

LGTM

lib/Target/ARM/ARMBaseInstrInfo.cpp
2830 ↗(On Diff #187007)

This change is necessary to prevent illegal reordering involving ADC/SBC, I guess? And this is covered by the test test_adc_mov in peephole-mi.mir? Maybe worth mentioning in the commit message.

This revision is now accepted and ready to land.Feb 19 2019, 11:11 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 25 2019, 7:52 AM