[ARM] Add some more missing T1 opcodes for the peephole optimisier

[dmgreen]

Summary

As pointed out in D57833, we can add a few extra Thumb1 opcodes
to the peephole optimisers ability to remove CMP instructions.

[efriedma]

LGTM

lib/Target/ARM/ARMBaseInstrInfo.cpp

2830 ↗

(On Diff #187007)

This change is necessary to prevent illegal reordering involving ADC/SBC, I guess? And this is covered by the test test_adc_mov in peephole-mi.mir? Maybe worth mentioning in the commit message.

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
   case ARM::tLSRrr:
   case ARM::tSUBrr:
   case ARM::tADDrr:
   case ARM::tADDi3:
   case ARM::tADDi8:
   case ARM::tSUBi3:
   case ARM::tSUBi8:
   case ARM::tMUL:
+  case ARM::tADC:
+  case ARM::tSBC:
+  case ARM::tRSB:
+  case ARM::tAND:
+  case ARM::tORR:
+  case ARM::tEOR:
+  case ARM::tBIC:
+  case ARM::tMVN:
+  case ARM::tASRri:
+  case ARM::tASRrr:
+  case ARM::tROR:
     IsThumb1 = true;
     LLVM_FALLTHROUGH;
   case ARM::RSBrr:
   case ARM::RSBri:
   case ARM::RSCrr:
   case ARM::RSCri:
   case ARM::ADDrr:
   case ARM::ADDri:
bool ARMBaseInstrInfo::optimizeCompareInstr(
   // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
   // However, if we only have MOVS instructions in between the CMP and the
   // other instruction (the MULS in this example), then the CPSR is dead so we
   // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
   // reordering and then continue the analysis hoping we can eliminate the
   // CMP. This peephole works on the vregs, so is still in SSA form. As a
   // consequence, the movs won't redefine/kill the MUL operands which would
   // make this reordering illegal.
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
   if (MI && IsThumb1) {
     --I;
+    if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
       bool CanReorder = true;
-    const bool HasStmts = I != E;
       for (; I != E; --I) {
         if (I->getOpcode() != ARM::tMOVi8) {
           CanReorder = false;
           break;
         }
       }
-    if (HasStmts && CanReorder) {
+      if (CanReorder) {
         MI = MI->removeFromParent();
         E = CmpInstr;
         CmpInstr.getParent()->insert(E, MI);
       }
+    }
     I = CmpInstr;
     E = MI;
   }
 
   // Check that CPSR isn't set between the comparison instruction and the one we
   // want to change. At the same time, search for SubAdd.
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
   bool SubAddIsThumb1 = false;
   do {
     const MachineInstr &Instr = *--I;
 
     // Check whether CmpInstr can be made redundant by the current instruction.
     if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr,
                              SubAddIsThumb1)) {
       SubAdd = &*I;

llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll

tailrecurse:                                      ; preds = %sw.bb, %entry
   %tmp2 = load i8*, i8** %scevgep5
   %0 = ptrtoint i8* %tmp2 to i32
 
 ; ARM:      ands {{r[0-9]+}}, {{r[0-9]+}}, #3
 ; ARM-NEXT: beq
 
 ; THUMB:      movs r[[R0:[0-9]+]], #3
 ; THUMB-NEXT: ands r[[R0]], r
-; THUMB-NEXT: cmp r[[R0]], #0
 ; THUMB-NEXT: beq
 
 ; T2:      ands {{r[0-9]+}}, {{r[0-9]+}}, #3
 ; T2-NEXT: beq
 
   %and = and i32 %0, 3
   %tst = icmp eq i32 %and, 0
   br i1 %tst, label %sw.bb, label %tailrecurse.switch

llvm/trunk/test/CodeGen/Thumb/peephole-mi.mir

+# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+--- |
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8m.base-none-none-eabi"
+
+  define i32 @test_adc(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_adc_mov(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_sbc(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_rsb(i32 %a) { ret i32 %a }
+  define i32 @test_and(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_orr(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_eor(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_bic(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_mvn(i32 %a) { ret i32 %a }
+  define i32 @test_asrrr(i32 %a, i32 %b) { ret i32 %a }
+  define i32 @test_asrri(i32 %a) { ret i32 %a }
+  define i32 @test_ror(i32 %a, i32 %b) { ret i32 %a }
+
+...
+---
+name:            test_adc
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_adc
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
+    %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_adc_mov
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_adc_mov
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
+  ; CHECK:   [[tMOVi8_:%[0-9]+]]:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+  ; CHECK:   tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
+    %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
+    %5:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_sbc
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_sbc
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
+    %2:tgpr, dead $cpsr = tSBC %0, %1, 14, $noreg, implicit $cpsr
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_rsb
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+body:             |
+  ; CHECK-LABEL: name: test_rsb
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %0:tgpr = COPY $r0
+    %1:tgpr, dead $cpsr = tRSB %0, 14, $noreg
+    tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %1
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_and
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_and
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tAND %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_orr
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_orr
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tORR %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_eor
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_eor
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tEOR %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_bic
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_bic
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tBIC %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_mvn
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+body:             |
+  ; CHECK-LABEL: name: test_mvn
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %0:tgpr = COPY $r0
+    %1:tgpr, dead $cpsr = tMVN %0, 14, $noreg
+    tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %1
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_asrrr
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_asrrr
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tASRrr %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_asrri
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+body:             |
+  ; CHECK-LABEL: name: test_asrri
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tASRri %0, 1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_ror
+liveins:
+  - { reg: '$r0', virtual-reg: '%0' }
+  - { reg: '$r1', virtual-reg: '%1' }
+body:             |
+  ; CHECK-LABEL: name: test_ror
+  ; CHECK:   [[COPY:%[0-9]+]]:tgpr = COPY $r1
+  ; CHECK:   [[COPY1:%[0-9]+]]:tgpr = COPY $r0
+  ; CHECK:   [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg
+  ; CHECK:   tBcc %bb.2, 1, $cpsr
+  ; CHECK:   tB %bb.1, 14, $noreg
+  bb.0:
+    successors: %bb.2(0x40000000), %bb.1(0x40000000)
+    liveins: $r0, $r1
+
+    %1:tgpr = COPY $r1
+    %0:tgpr = COPY $r0
+    %2:tgpr, dead $cpsr = tROR %0, %1, 14, $noreg
+    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 1, $cpsr
+    tB %bb.1, 14, $noreg
+
+  bb.1:
+    $r0 = COPY %0
+    tBX_RET 14, $noreg, implicit $r0
+
+  bb.2:
+    %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
+    $r0 = COPY %2
+    tBX_RET 14, $noreg, implicit $r0
+...

llvm/trunk/test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll

 ; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    str r1, [sp, #48] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r0, [sp, #124]
 ; THUMBV6-NEXT:    str r0, [sp, #80] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r1, r5
 ; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [sp, #24] @ 4-byte Spill
 ; THUMBV6-NEXT:    adds r6, r0, r6
 ; THUMBV6-NEXT:    str r4, [sp, #68] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r0, r4
 ; THUMBV6-NEXT:    mov r1, r5
 ; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    str r0, [sp, #20] @ 4-byte Spill
 ; THUMBV6-NEXT:    adds r0, r1, r6
 ; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r0, r5
 ; THUMBV6-NEXT:    adcs r0, r5
-; THUMBV6-NEXT:    str r0, [sp, #64] @ 4-byte Spill
-; THUMBV6-NEXT:    ldr r7, [sp, #104]
+; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r4, [sp, #104]
 ; THUMBV6-NEXT:    ldr r0, [sp, #72] @ 4-byte Reload
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r7
+; THUMBV6-NEXT:    mov r2, r4
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    str r1, [sp, #52] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r0, [sp, #108]
-; THUMBV6-NEXT:    str r0, [sp, #60] @ 4-byte Spill
+; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    ldr r4, [sp, #44] @ 4-byte Reload
-; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    ldr r7, [sp, #44] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
-; THUMBV6-NEXT:    str r1, [sp, #32] @ 4-byte Spill
+; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
 ; THUMBV6-NEXT:    adds r6, r0, r6
-; THUMBV6-NEXT:    str r7, [sp, #24] @ 4-byte Spill
-; THUMBV6-NEXT:    mov r0, r7
+; THUMBV6-NEXT:    str r4, [sp, #64] @ 4-byte Spill
+; THUMBV6-NEXT:    mov r0, r4
 ; THUMBV6-NEXT:    mov r1, r5
-; THUMBV6-NEXT:    mov r2, r4
+; THUMBV6-NEXT:    mov r2, r7
 ; THUMBV6-NEXT:    mov r3, r5
 ; THUMBV6-NEXT:    bl __aeabi_lmul
 ; THUMBV6-NEXT:    adds r1, r1, r6
 ; THUMBV6-NEXT:    mov r2, r5
 ; THUMBV6-NEXT:    adcs r2, r5
 ; THUMBV6-NEXT:    str r2, [sp, #44] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r2, [sp, #20] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r0, r2
 ; THUMBV6-NEXT:    ldr r2, [sp, #16] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r1, r2
 ; THUMBV6-NEXT:    ldr r2, [sp, #36] @ 4-byte Reload
 ; THUMBV6-NEXT:    adds r0, r2, r0
 ; THUMBV6-NEXT:    ldr r2, [sp, #76] @ 4-byte Reload
 ; THUMBV6-NEXT:    str r0, [r2, #8]
 ; THUMBV6-NEXT:    ldr r0, [sp, #40] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r1, r0
 ; THUMBV6-NEXT:    str r1, [r2, #12]
-; THUMBV6-NEXT:    ldr r1, [sp, #28] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
 ; THUMBV6-NEXT:    adcs r5, r5
 ; THUMBV6-NEXT:    movs r0, #1
 ; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r2, r0
 ; THUMBV6-NEXT:    bne .LBB0_2
 ; THUMBV6-NEXT:  @ %bb.1: @ %start
 ; THUMBV6-NEXT:    mov r2, r1
 ; THUMBV6-NEXT:  .LBB0_2: @ %start
 ; THUMBV6-NEXT:    str r2, [sp, #40] @ 4-byte Spill
 ; THUMBV6-NEXT:    ldr r1, [sp, #56] @ 4-byte Reload
 ; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r4, r0
 ; THUMBV6-NEXT:    bne .LBB0_4
 ; THUMBV6-NEXT:  @ %bb.3: @ %start
 ; THUMBV6-NEXT:    mov r4, r1
 ; THUMBV6-NEXT:  .LBB0_4: @ %start
 ; THUMBV6-NEXT:    ldr r1, [sp, #80] @ 4-byte Reload
 ; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r2, r0
 ; THUMBV6-NEXT:    ldr r3, [sp, #48] @ 4-byte Reload
-; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r7, [sp, #28] @ 4-byte Reload
 ; THUMBV6-NEXT:    bne .LBB0_6
 ; THUMBV6-NEXT:  @ %bb.5: @ %start
 ; THUMBV6-NEXT:    ldr r2, [sp, #80] @ 4-byte Reload
 ; THUMBV6-NEXT:  .LBB0_6: @ %start
 ; THUMBV6-NEXT:    cmp r3, #0
-; THUMBV6-NEXT:    mov r7, r0
+; THUMBV6-NEXT:    mov r6, r0
 ; THUMBV6-NEXT:    ldr r1, [sp, #72] @ 4-byte Reload
 ; THUMBV6-NEXT:    bne .LBB0_8
 ; THUMBV6-NEXT:  @ %bb.7: @ %start
-; THUMBV6-NEXT:    mov r7, r3
+; THUMBV6-NEXT:    mov r6, r3
 ; THUMBV6-NEXT:  .LBB0_8: @ %start
-; THUMBV6-NEXT:    cmp r6, #0
+; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
+; THUMBV6-NEXT:    ldr r6, [sp, #32] @ 4-byte Reload
+; THUMBV6-NEXT:    cmp r7, #0
 ; THUMBV6-NEXT:    mov r3, r0
 ; THUMBV6-NEXT:    bne .LBB0_10
 ; THUMBV6-NEXT:  @ %bb.9: @ %start
-; THUMBV6-NEXT:    mov r3, r6
+; THUMBV6-NEXT:    mov r3, r7
 ; THUMBV6-NEXT:  .LBB0_10: @ %start
 ; THUMBV6-NEXT:    cmp r1, #0
-; THUMBV6-NEXT:    mov r6, r1
+; THUMBV6-NEXT:    mov r7, r1
 ; THUMBV6-NEXT:    mov r1, r0
 ; THUMBV6-NEXT:    bne .LBB0_12
 ; THUMBV6-NEXT:  @ %bb.11: @ %start
-; THUMBV6-NEXT:    mov r1, r6
+; THUMBV6-NEXT:    mov r1, r7
 ; THUMBV6-NEXT:  .LBB0_12: @ %start
-; THUMBV6-NEXT:    str r7, [sp, #72] @ 4-byte Spill
 ; THUMBV6-NEXT:    ands r2, r4
-; THUMBV6-NEXT:    ldr r6, [sp, #60] @ 4-byte Reload
+; THUMBV6-NEXT:    mov r7, r6
 ; THUMBV6-NEXT:    cmp r6, #0
 ; THUMBV6-NEXT:    mov r4, r0
 ; THUMBV6-NEXT:    bne .LBB0_14
 ; THUMBV6-NEXT:  @ %bb.13: @ %start
-; THUMBV6-NEXT:    mov r4, r6
+; THUMBV6-NEXT:    mov r4, r7
 ; THUMBV6-NEXT:  .LBB0_14: @ %start
-; THUMBV6-NEXT:    ldr r7, [sp, #40] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r2, r7
+; THUMBV6-NEXT:    ldr r6, [sp, #40] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r2, r6
 ; THUMBV6-NEXT:    ands r4, r1
 ; THUMBV6-NEXT:    orrs r4, r3
 ; THUMBV6-NEXT:    ldr r3, [sp, #52] @ 4-byte Reload
 ; THUMBV6-NEXT:    cmp r3, #0
 ; THUMBV6-NEXT:    mov r1, r0
 ; THUMBV6-NEXT:    bne .LBB0_16
 ; THUMBV6-NEXT:  @ %bb.15: @ %start
 ; THUMBV6-NEXT:    mov r1, r3
 ; THUMBV6-NEXT:  .LBB0_16: @ %start
-; THUMBV6-NEXT:    ldr r3, [sp, #72] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r3, [sp, #56] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r2, r3
 ; THUMBV6-NEXT:    orrs r4, r1
 ; THUMBV6-NEXT:    ldr r1, [sp, #68] @ 4-byte Reload
 ; THUMBV6-NEXT:    ldr r3, [sp, #80] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r1, r3
-; THUMBV6-NEXT:    cmp r1, #0
 ; THUMBV6-NEXT:    mov r3, r0
 ; THUMBV6-NEXT:    bne .LBB0_18
 ; THUMBV6-NEXT:  @ %bb.17: @ %start
 ; THUMBV6-NEXT:    mov r3, r1
 ; THUMBV6-NEXT:  .LBB0_18: @ %start
-; THUMBV6-NEXT:    ldr r1, [sp, #64] @ 4-byte Reload
+; THUMBV6-NEXT:    ldr r1, [sp, #60] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r2, r1
 ; THUMBV6-NEXT:    ldr r1, [sp, #44] @ 4-byte Reload
 ; THUMBV6-NEXT:    orrs r4, r1
-; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
-; THUMBV6-NEXT:    orrs r1, r6
-; THUMBV6-NEXT:    mov r6, r1
-; THUMBV6-NEXT:    cmp r1, #0
+; THUMBV6-NEXT:    ldr r6, [sp, #64] @ 4-byte Reload
+; THUMBV6-NEXT:    orrs r6, r7
 ; THUMBV6-NEXT:    mov r1, r0
 ; THUMBV6-NEXT:    bne .LBB0_20
 ; THUMBV6-NEXT:  @ %bb.19: @ %start
 ; THUMBV6-NEXT:    mov r1, r6
 ; THUMBV6-NEXT:  .LBB0_20: @ %start
 ; THUMBV6-NEXT:    ands r1, r3
 ; THUMBV6-NEXT:    orrs r1, r4
 ; THUMBV6-NEXT:    orrs r1, r2