[PowerPC] Code Cleanup Remove u1imm

[stefanp]

Summary

The type i1imm serves the same purpose as u1imm. Both types are not required.

This patch removes the u1imm type.

[hfinkel]

LGTM. I suppose that I thought that this was needed at some point to parse (1, 0) instead of (-1, 0), but if this is not needed in practice, then it should be simplified.

[stefanp]

Hi Hal,
Thank you for the review.
I've looked around but the only place we use u1imm is where we only have 1 bit to use in the instruction anyway so we have no way to represent -1 anyway.

[hfinkel]

In D57759#1385950, @stefanp wrote:

Hi Hal,
Thank you for the review.
I've looked around but the only place we use u1imm is where we only have 1 bit to use in the instruction anyway so we have no way to represent -1 anyway.

Okay. This is just a question of parsing and text formatting. A 1-bit signed number is -1 or 0, and an unsigned 1-bit number is 1 or 0.

[stefanp]

Hi Hal,
I'm actually not going to do this in the end.... I'm just going to abandon this patch.
I realized that we did actually need this type too.

The u1imm type is actually an i32 which is later restricted to be either a 0 or a 1. On the other hand the i1imm type is an i1. This is an important difference.

The issue is that some of the instructions that use this type have builtins. For example: vshasigmaw. The builtin requires that the single bit be passed in as a parameter and that means we need to use an i32. Anyway I'm going to leave the type in.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

unsigned getCRBitMask() const {
     assert(isCRBitMask() && "Invalid access!");
     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
   }
 
   bool isToken() const override { return Kind == Token; }
   bool isImm() const override {
     return Kind == Immediate || Kind == Expression;
   }
-  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
   bool isU6ImmX2() const { return Kind == Immediate &&
                                   isUInt<6>(getImm()) &&

llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h

void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
                                unsigned PrintMethodIdx,
                                raw_ostream &OS);
 
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printPredicateOperand(const MCInst *MI, unsigned OpNo,
                              raw_ostream &O, const char *Modifier = nullptr);
   void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
-  void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned Code = MI->getOperand(OpNo).getImm();
   if (Code == 2)
     O << "-";
   else if (Code == 3)
     O << "+";
 }
 
-void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
-                                       raw_ostream &O) {
-  unsigned int Value = MI->getOperand(OpNo).getImm();
-  assert(Value <= 1 && "Invalid u1imm argument!");
-  O << (unsigned int)Value;
-}
-
 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   unsigned int Value = MI->getOperand(OpNo).getImm();
   assert(Value <= 3 && "Invalid u2imm argument!");
   O << (unsigned int)Value;
 }
 
 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def CMPLD  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
                             "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
   def CMPDI  : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
                            "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
   def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                            "cmpldi $dst, $src1, $src2",
                            IIC_IntCompare>, isPPC64;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
-                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
+                                (ins i1imm:$L, g8rc:$rA, g8rc:$rB),
                                 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
                Requires<[IsISA3_0]>;
   def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF),
                              (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB",
                              IIC_IntCompare, []>, Requires<[IsISA3_0]>;
 }
 
 let hasSideEffects = 0 in {

 
 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
 def : Pat<(atomic_store_64 xaddr:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
 
 let Predicates = [IsISA3_0] in {
 
 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
                    InstrItinClass itin, list<dag> pattern>
-  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
+  : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, i1imm:$L),
                  !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_L1_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8  : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
 def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
 }
 
 // SLB Invalidate Entry Global
 def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
                       "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
              [(set OutTy:$vD, (IntID InTy:$vB))]>;
 
 class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
   : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
              !strconcat(opc, " $vD, $vA"), IIC_VecFP,
              [(set Ty:$vD, (IntID Ty:$vA))]>;
 
 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
-  : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
+  : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, i1imm:$ST, u4imm:$SIX),
               !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
               [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction Definitions.
 
 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
 let Predicates = [HasAltivec] in {

 def VMUL10EUQ  : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
 def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
 
 // Decimal Integer Format Conversion Instructions
 
 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
 class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
                                list<dag> pattern>
-  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
+  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, i1imm:$PS),
                         !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
   let Defs = [CR6];
 }
 
 // [PO VRT EO VRB 1 / XO]
 class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
                            list<dag> pattern>
   : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),

 let Defs = [CR6] in
 def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
 
 def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
 
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
 class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo,
-                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
+                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, i1imm:$PS),
                    !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
   let Defs = [CR6];
 }
 
 // [PO VRT VRA VRB 1 / XO]
 class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {

llvm/lib/Target/PowerPC/PPCInstrHTM.td

 let hasSideEffects = 1 in {
 def TCHECK_RET : PPCCustomInserterPseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>;
 }
 
 
 let Predicates = [HasHTM] in {
 
 def TBEGIN : XForm_htm0 <31, 654,
-                         (outs crrc0:$ret), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
+                         (outs crrc0:$ret), (ins i1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
 
 def TEND : XForm_htm1 <31, 686,
-                       (outs crrc0:$ret), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
+                       (outs crrc0:$ret), (ins i1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
 
 def TABORT : XForm_base_r3xo <31, 910,
                               (outs crrc0:$ret), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
                               []>, isDOT {
   let RST = 0;
   let B = 0;
 }
 
def TABORTDC : XForm_base_r3xo <31, 814,
                                 isDOT;
 
 def TABORTDCI : XForm_base_r3xo <31, 878,
                                  (outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
                                  "tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>,
                                  isDOT;
 
 def TSR : XForm_htm2 <31, 750,
-                      (outs crrc0:$ret), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
+                      (outs crrc0:$ret), (ins i1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
                       isDOT;
 
 def TCHECK : XForm_htm3 <31, 718,
                         (outs), (ins crrc:$BF), "tcheck $BF", IIC_SprMTSPR, []>;
 
 
 def TRECLAIM : XForm_base_r3xo <31, 942,
                                 (outs crrc:$ret), (ins gprc:$A), "treclaim. $A",

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }
 def PPCRegSPE4RCAsmOperand : AsmOperandClass {
   let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber";
 }
 def spe4rc : RegisterOperand<SPE4RC> {
   let ParserMatchClass = PPCRegSPE4RCAsmOperand;
 }
 
-def PPCU1ImmAsmOperand : AsmOperandClass {
-  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
-  let RenderMethod = "addImmOperands";
-}
-def u1imm   : Operand<i32> {
-  let PrintMethod = "printU1ImmOperand";
-  let ParserMatchClass = PPCU1ImmAsmOperand;
-}
-
 def PPCU2ImmAsmOperand : AsmOperandClass {
   let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
   let RenderMethod = "addImmOperands";
 }
 def u2imm   : Operand<i32> {
   let PrintMethod = "printU2ImmOperand";
   let ParserMatchClass = PPCU2ImmAsmOperand;
 }

 // interferes with necessary special handling (see PPCFastISel.cpp).
 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
                          (ins u10imm:$imm, u10imm:$dmy),
                          "mfbhrbe $rD, $imm", IIC_BrB,
                          [(set i32:$rD,
                                (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
                          PPC970_DGroup_First;
 
-def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
+def RFEBB : XLForm_S<19, 146, (outs), (ins i1imm:$imm), "rfebb $imm",
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
 // DCB* instructions.
 def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
                       IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",

 }
 
 let isCompare = 1, hasSideEffects = 0 in {
   def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
                           "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
   def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
                            "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
   def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
-                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
+                                (ins i1imm:$L, g8rc:$rA, g8rc:$rB),
                                 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
                Requires<[IsISA3_0]>;
 }
 }
 
 let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
 let isCommutable = 1 in {
 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // separate pattern so that it can convert the input register class from
   // VRRC(v8i16) to VSRC.
   def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)),
             (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>;
 
   class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
                                 list<dag> pattern>
     : Z23Form_8<opcode, xo,
-                (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
+                (outs vrrc:$vT), (ins i1imm:$r, vrrc:$vB, u2imm:$rmc),
                 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
     let RC = ex;
   }
 
   // Round to Quad-Precision Integer [with Inexact]
   def XSRQPI   : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 0, "xsrqpi" , []>;
   def XSRQPIX  : Z23_VT5_R1_VB5_RMC2_EX1<63,  5, 1, "xsrqpix", []>;