This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Allow constructing SrcOp/DstOp from MachineOperand
ClosedPublic

Authored by arsenm on Feb 4 2019, 5:52 AM.

Download Raw Diff

Details

Reviewers

aditya_nandakumar
aemerson
dsanders
paquette
volkan

Diff Detail

Event Timeline

arsenm created this revision.Feb 4 2019, 5:52 AM

Herald added subscribers: Petar.Avramovic, kristof.beyls, rovka, wdng. · View Herald TranscriptFeb 4 2019, 5:52 AM

Please add a test case. LGTM.

This revision is now accepted and ready to land.Feb 4 2019, 6:44 AM

r353080

Revision Contents

Path

Size

include/

llvm/

CodeGen/

GlobalISel/

MachineIRBuilder.h

2 lines

Diff 185034

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	union {
LLT LLTTy;		LLT LLTTy;
unsigned Reg;		unsigned Reg;
const TargetRegisterClass *RC;		const TargetRegisterClass *RC;
};		};

public:		public:
enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };		enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}		DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
		DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}		DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}		DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}

void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {		void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
switch (Ty) {		switch (Ty) {
case DstType::Ty_Reg:		case DstType::Ty_Reg:
MIB.addDef(Reg);		MIB.addDef(Reg);
break;		break;
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines	union {
MachineInstrBuilder SrcMIB;		MachineInstrBuilder SrcMIB;
unsigned Reg;		unsigned Reg;
CmpInst::Predicate Pred;		CmpInst::Predicate Pred;
};		};

public:		public:
enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };		enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}		SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
		SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}		SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}		SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}

void addSrcToMIB(MachineInstrBuilder &MIB) const {		void addSrcToMIB(MachineInstrBuilder &MIB) const {
switch (Ty) {		switch (Ty) {
case SrcType::Ty_Predicate:		case SrcType::Ty_Predicate:
MIB.addPredicate(Pred);		MIB.addPredicate(Pred);
break;		break;
▲ Show 20 Lines • Show All 1,084 Lines • Show Last 20 Lines