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GlobalISel: Implement fewerElementsVector for shifts
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Authored by arsenm on Jan 30 2019, 2:48 PM.

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Details

Reviewers

dsanders
paquette
aemerson
volkan
aditya_nandakumar

Summary

Introduce a new function which handles instructions with multiple type
indices, but have the same number of vector elements.

Also legalize v2s16 shifts when applicable.

Diff Detail

Event Timeline

arsenm created this revision.Jan 30 2019, 2:48 PM

Herald added subscribers: Petar.Avramovic, tschuett, kristof.beyls and 4 others. · View Herald TranscriptJan 30 2019, 2:48 PM

aemerson added inline comments.Feb 1 2019, 4:04 PM

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
161	type type
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1761	I'm finding it difficult to tell exactly what this function is trying to do. Can we have some comments throughout to explain what each phase is trying to achieve, with a small example if it's not clear enough from prose.
1795	We can return 0 here to fall back instead of dying.

arsenm marked 2 inline comments as done.Feb 5 2019, 9:16 AM

arsenm added inline comments.

lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1795	Is it OK I fa failed legalization created dead instructions?

arsenm marked an inline comment as done.Feb 5 2019, 9:50 AM

arsenm added inline comments.

lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1795	This should also consistently fail along with getNarrowTypeBreakDown, previously checked

Try to add better comments and rename function

Thanks, it looks better now.

lib/CodeGen/GlobalISel/LegalizerHelper.cpp
1795	If legalization fails then the resulting MF is usually invalid and deleted anyway.

This revision is now accepted and ready to land.Feb 6 2019, 3:20 PM

r353432

Revision Contents

Path

Size

include/

llvm/

CodeGen/

GlobalISel/

LegalizerHelper.h

6 lines

lib/

CodeGen/

GlobalISel/

LegalizerHelper.cpp

160 lines

Target/

AMDGPU/

AMDGPULegalizerInfo.cpp

9 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

legalize-ashr.mir

439 lines

legalize-lshr.mir

439 lines

legalize-shl.mir

493 lines

Diff 185338

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines	private:
LegalizeResult fewerElementsVectorImplicitDef(MachineInstr &MI,		LegalizeResult fewerElementsVectorImplicitDef(MachineInstr &MI,
unsigned TypeIdx, LLT NarrowTy);		unsigned TypeIdx, LLT NarrowTy);

/// Legalize a simple vector instruction where all operands are the same type		/// Legalize a simple vector instruction where all operands are the same type
/// by splitting into multiple components.		/// by splitting into multiple components.
LegalizeResult fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,		LegalizeResult fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
LLT NarrowTy);		LLT NarrowTy);

		/// Legalize a instruction with a vector type where each operand may have a
		/// different element type. All type indexes must have the same number of
		aemersonUnsubmitted Done Reply Inline Actions type type aemerson: type type
		/// elements.
		LegalizeResult fewerElementsVectorMultiEltType(MachineInstr &MI,
		unsigned TypeIdx, LLT NarrowTy);

LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,		LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
LLT NarrowTy);		LLT NarrowTy);

LegalizeResult		LegalizeResult
fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);		fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);

LegalizeResult		LegalizeResult
fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);		fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
Show All 25 Lines

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show All 23 Lines
#include "llvm/Support/MathExtras.h"		#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"

#define DEBUG_TYPE "legalizer"		#define DEBUG_TYPE "legalizer"

using namespace llvm;		using namespace llvm;
using namespace LegalizeActions;		using namespace LegalizeActions;

		/// Try to break down \p OrigTy into \p NarrowTy sized pieces.
		///
		/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
		/// with any leftover piece as type \p LeftoverTy
		///
		/// Returns -1 if the breakdown is not satisfiable.
		static int getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
		assert(!LeftoverTy.isValid() && "this is an out argument");

		unsigned Size = OrigTy.getSizeInBits();
		unsigned NarrowSize = NarrowTy.getSizeInBits();
		unsigned NumParts = Size / NarrowSize;
		unsigned LeftoverSize = Size - NumParts * NarrowSize;
		assert(Size > NarrowSize);

		if (LeftoverSize == 0)
		return NumParts;

		if (NarrowTy.isVector()) {
		unsigned EltSize = OrigTy.getScalarSizeInBits();
		if (LeftoverSize % EltSize != 0)
		return -1;
		LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
		} else {
		LeftoverTy = LLT::scalar(LeftoverSize);
		}

		return NumParts;
		}

LegalizerHelper::LegalizerHelper(MachineFunction &MF,		LegalizerHelper::LegalizerHelper(MachineFunction &MF,
GISelChangeObserver &Observer,		GISelChangeObserver &Observer,
MachineIRBuilder &Builder)		MachineIRBuilder &Builder)
: MIRBuilder(Builder), MRI(MF.getRegInfo()),		: MIRBuilder(Builder), MRI(MF.getRegInfo()),
LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {		LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
MIRBuilder.setMF(MF);		MIRBuilder.setMF(MF);
MIRBuilder.setChangeObserver(Observer);		MIRBuilder.setChangeObserver(Observer);
}		}
▲ Show 20 Lines • Show All 1,683 Lines • ▼ Show 20 Lines	if (NarrowTy.isVector())
MIRBuilder.buildConcatVectors(DstReg, DstRegs);		MIRBuilder.buildConcatVectors(DstReg, DstRegs);
else		else
MIRBuilder.buildBuildVector(DstReg, DstRegs);		MIRBuilder.buildBuildVector(DstReg, DstRegs);

MI.eraseFromParent();		MI.eraseFromParent();
return Legalized;		return Legalized;
}		}

		// Handle splitting vector operations which need to have the same number of
		aemersonUnsubmitted Not Done Reply Inline Actions I'm finding it difficult to tell exactly what this function is trying to do. Can we have some comments throughout to explain what each phase is trying to achieve, with a small example if it's not clear enough from prose. aemerson: I'm finding it difficult to tell exactly what this function is trying to do. Can we have some…
		// elements in each type index, but each type index may have a different element
		// type.
		//
		// e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
		// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
		// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
		//
		// Also handles some irregular breakdown cases, e.g.
		// e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
		// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
		// s64 = G_SHL s64, s32
		LegalizerHelper::LegalizeResult
		LegalizerHelper::fewerElementsVectorMultiEltType(
		MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
		if (TypeIdx != 0)
		return UnableToLegalize;

		const LLT NarrowTy0 = NarrowTyArg;
		const unsigned NewNumElts =
		NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;

		const unsigned DstReg = MI.getOperand(0).getReg();
		LLT DstTy = MRI.getType(DstReg);
		LLT LeftoverTy0;

		// All of the operands need to have the same number of elements, so if we can
		// determine a type breakdown for the result type, we can for all of the
		// source types.
		int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
		if (NumParts < 0)
		return UnableToLegalize;

		SmallVector<MachineInstrBuilder, 4> NewInsts;

		aemersonUnsubmitted Not Done Reply Inline Actions We can return 0 here to fall back instead of dying. aemerson: We can return 0 here to fall back instead of dying.
		arsenmAuthorUnsubmitted Done Reply Inline Actions Is it OK I fa failed legalization created dead instructions? arsenm: Is it OK I fa failed legalization created dead instructions?
		arsenmAuthorUnsubmitted Done Reply Inline Actions This should also consistently fail along with getNarrowTypeBreakDown, previously checked arsenm: This should also consistently fail along with getNarrowTypeBreakDown, previously checked
		aemersonUnsubmitted Not Done Reply Inline Actions If legalization fails then the resulting MF is usually invalid and deleted anyway. aemerson: If legalization fails then the resulting MF is usually invalid and deleted anyway.
		SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
		SmallVector<unsigned, 4> PartRegs, LeftoverRegs;

		for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
		LLT LeftoverTy;
		unsigned SrcReg = MI.getOperand(I).getReg();
		LLT SrcTyI = MRI.getType(SrcReg);
		LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
		LLT LeftoverTyI;

		// Split this operand into the requested typed registers, and any leftover
		// required to reproduce the original type.
		if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
		LeftoverRegs))
		return UnableToLegalize;

		if (I == 1) {
		// For the first operand, create an instruction for each part and setup
		// the result.
		for (unsigned PartReg : PartRegs) {
		unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
		NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
		.addDef(PartDstReg)
		.addUse(PartReg));
		DstRegs.push_back(PartDstReg);
		}

		for (unsigned LeftoverReg : LeftoverRegs) {
		unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
		NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
		.addDef(PartDstReg)
		.addUse(LeftoverReg));
		LeftoverDstRegs.push_back(PartDstReg);
		}
		} else {
		assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());

		// Add the newly created operand splits to the existing instructions. The
		// odd-sized pieces are ordered after the requested NarrowTyArg sized
		// pieces.
		unsigned InstCount = 0;
		for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
		NewInsts[InstCount++].addUse(PartRegs[J]);
		for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
		NewInsts[InstCount++].addUse(LeftoverRegs[J]);
		}

		PartRegs.clear();
		LeftoverRegs.clear();
		}

		// Insert the newly built operations and rebuild the result register.
		for (auto &MIB : NewInsts)
		MIRBuilder.insertInstr(MIB);

		insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);

		MI.eraseFromParent();
		return Legalized;
		}

LegalizerHelper::LegalizeResult		LegalizerHelper::LegalizeResult
LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,		LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
LLT NarrowTy) {		LLT NarrowTy) {
if (TypeIdx != 0)		if (TypeIdx != 0)
return UnableToLegalize;		return UnableToLegalize;

unsigned DstReg = MI.getOperand(0).getReg();		unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcReg = MI.getOperand(1).getReg();		unsigned SrcReg = MI.getOperand(1).getReg();
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines	if (NarrowTy0.isVector())
MIRBuilder.buildConcatVectors(DstReg, DstRegs);		MIRBuilder.buildConcatVectors(DstReg, DstRegs);
else		else
MIRBuilder.buildBuildVector(DstReg, DstRegs);		MIRBuilder.buildBuildVector(DstReg, DstRegs);

MI.eraseFromParent();		MI.eraseFromParent();
return Legalized;		return Legalized;
}		}

/// Try to break down \p OrigTy into \p NarrowTy sized pieces.
///
/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
/// with any leftover piece as type \p LeftoverTy
///
/// Returns -1 if the breakdown is not satisfiable.
static int getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
assert(!LeftoverTy.isValid() && "this is an out argument");

unsigned Size = OrigTy.getSizeInBits();
unsigned NarrowSize = NarrowTy.getSizeInBits();
unsigned NumParts = Size / NarrowSize;
unsigned LeftoverSize = Size - NumParts * NarrowSize;
assert(Size > NarrowSize);

if (LeftoverSize == 0)
return NumParts;

if (NarrowTy.isVector()) {
unsigned EltSize = OrigTy.getScalarSizeInBits();
if (LeftoverSize % EltSize != 0)
return -1;
LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
} else {
LeftoverTy = LLT::scalar(LeftoverSize);
}

return NumParts;
}

LegalizerHelper::LegalizeResult		LegalizerHelper::LegalizeResult
LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,		LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
LLT NarrowTy) {		LLT NarrowTy) {
// FIXME: Don't know how to handle secondary types yet.		// FIXME: Don't know how to handle secondary types yet.
if (TypeIdx != 0)		if (TypeIdx != 0)
return UnableToLegalize;		return UnableToLegalize;

MachineMemOperand MMO = MI.memoperands_begin();		MachineMemOperand MMO = MI.memoperands_begin();
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines	LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_FCEIL:		case G_FCEIL:
case G_INTRINSIC_ROUND:		case G_INTRINSIC_ROUND:
case G_INTRINSIC_TRUNC:		case G_INTRINSIC_TRUNC:
case G_FCOS:		case G_FCOS:
case G_FSIN:		case G_FSIN:
case G_FSQRT:		case G_FSQRT:
case G_BSWAP:		case G_BSWAP:
return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);		return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
		case G_SHL:
		case G_LSHR:
		case G_ASHR:
		return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
case G_ZEXT:		case G_ZEXT:
case G_SEXT:		case G_SEXT:
case G_ANYEXT:		case G_ANYEXT:
case G_FPEXT:		case G_FPEXT:
case G_FPTRUNC:		case G_FPTRUNC:
case G_SITOFP:		case G_SITOFP:
case G_UITOFP:		case G_UITOFP:
case G_FPTOSI:		case G_FPTOSI:
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Lines	getActionDefinitionsBuilder(G_SELECT)
.clampMaxNumElements(0, PrivatePtr, 2)		.clampMaxNumElements(0, PrivatePtr, 2)
.legalIf(all(isPointer(0), typeIs(1, S1)));		.legalIf(all(isPointer(0), typeIs(1, S1)));

// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can		// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
// be more flexible with the shift amount type.		// be more flexible with the shift amount type.
auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})		auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
.legalFor({{S32, S32}, {S64, S32}});		.legalFor({{S32, S32}, {S64, S32}});
if (ST.has16BitInsts()) {		if (ST.has16BitInsts()) {
		if (ST.hasVOP3PInsts()) {
		Shifts.legalFor({{S16, S32}, {S16, S16}, {V2S16, V2S16}})
		.clampMaxNumElements(0, S16, 2);
		} else
Shifts.legalFor({{S16, S32}, {S16, S16}});		Shifts.legalFor({{S16, S32}, {S16, S16}});
Shifts.clampScalar(0, S16, S64);		Shifts.clampScalar(0, S16, S64);
} else		} else
Shifts.clampScalar(0, S32, S64);		Shifts.clampScalar(0, S32, S64);
Shifts.clampScalar(1, S32, S32);		Shifts.clampScalar(1, S32, S32)
		.scalarize(0);

for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {		for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
unsigned VecTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 1 : 0;		unsigned VecTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 1 : 0;
unsigned EltTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 0 : 1;		unsigned EltTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 0 : 1;
unsigned IdxTypeIdx = 2;		unsigned IdxTypeIdx = 2;

getActionDefinitionsBuilder(Op)		getActionDefinitionsBuilder(Op)
.legalIf([=](const LegalityQuery &Query) {		.legalIf([=](const LegalityQuery &Query) {
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: test_ashr_i32_i32		name: test_ashr_s32_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_ashr_i32_i32		; SI-LABEL: name: test_ashr_s32_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)		; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_i32_i32		; VI-LABEL: name: test_ashr_s32_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)		; VI: $vgpr0 = COPY [[ASHR]](s32)
; GFX9-LABEL: name: test_ashr_i32_i32		; GFX9-LABEL: name: test_ashr_s32_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)		; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_ASHR %0, %1		%2:_(s32) = G_ASHR %0, %1
$vgpr0 = COPY %2		$vgpr0 = COPY %2
...		...
---		---
name: test_ashr_i64_i64		name: test_ashr_s64_s64
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

; SI-LABEL: name: test_ashr_i64_i64		; SI-LABEL: name: test_ashr_s64_s64
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; VI-LABEL: name: test_ashr_i64_i64		; VI-LABEL: name: test_ashr_s64_s64
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX9-LABEL: name: test_ashr_i64_i64		; GFX9-LABEL: name: test_ashr_s64_s64
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3		%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_ASHR %0, %1		%2:_(s64) = G_ASHR %0, %1
$vgpr0_vgpr1 = COPY %2		$vgpr0_vgpr1 = COPY %2
...		...
---		---
name: test_ashr_i64_i32		name: test_ashr_s64_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2		liveins: $vgpr0_vgpr1, $vgpr2

; SI-LABEL: name: test_ashr_i64_i32		; SI-LABEL: name: test_ashr_s64_s32
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; VI-LABEL: name: test_ashr_i64_i32		; VI-LABEL: name: test_ashr_s64_s32
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX9-LABEL: name: test_ashr_i64_i32		; GFX9-LABEL: name: test_ashr_s64_s32
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2		%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_ASHR %0, %1		%2:_(s64) = G_ASHR %0, %1
$vgpr0_vgpr1 = COPY %2		$vgpr0_vgpr1 = COPY %2
...		...
---		---
name: test_ashr_i64_i16		name: test_ashr_s64_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2		liveins: $vgpr0_vgpr1, $vgpr2

; SI-LABEL: name: test_ashr_i64_i16		; SI-LABEL: name: test_ashr_s64_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; VI-LABEL: name: test_ashr_i64_i16		; VI-LABEL: name: test_ashr_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX9-LABEL: name: test_ashr_i64_i16		; GFX9-LABEL: name: test_ashr_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2		%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1		%2:_(s16) = G_TRUNC %1
%3:_(s64) = G_ASHR %0, %2		%3:_(s64) = G_ASHR %0, %2
$vgpr0_vgpr1 = COPY %3		$vgpr0_vgpr1 = COPY %3
...		...

---		---
name: test_ashr_i16_i32		name: test_ashr_s16_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_ashr_i16_i32		; SI-LABEL: name: test_ashr_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY3]](s32)		; SI: $vgpr0 = COPY [[COPY3]](s32)
; VI-LABEL: name: test_ashr_i16_i32		; VI-LABEL: name: test_ashr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i16_i32		; GFX9-LABEL: name: test_ashr_s16_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0		%2:_(s16) = G_TRUNC %0
%3:_(s16) = G_ASHR %2, %1		%3:_(s16) = G_ASHR %2, %1
%4:_(s32) = G_ANYEXT %3		%4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4		$vgpr0 = COPY %4
...		...

---		---
name: test_ashr_i16_i16		name: test_ashr_s16_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_ashr_i16_i16		; SI-LABEL: name: test_ashr_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)		; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)		; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_i16_i16		; VI-LABEL: name: test_ashr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i16_i16		; GFX9-LABEL: name: test_ashr_s16_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)		; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0		%2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1		%3:_(s16) = G_TRUNC %1
%4:_(s16) = G_ASHR %2, %3		%4:_(s16) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4		%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5		$vgpr0 = COPY %5
...		...

---		---
name: test_ashr_i16_i8		name: test_ashr_s16_i8
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_ashr_i16_i8		; SI-LABEL: name: test_ashr_s16_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)		; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)		; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_i16_i8		; VI-LABEL: name: test_ashr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i16_i8		; GFX9-LABEL: name: test_ashr_s16_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)		; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	bb.0:
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0		%2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1		%3:_(s8) = G_TRUNC %1
%4:_(s8) = G_ASHR %2, %3		%4:_(s8) = G_ASHR %2, %3
%5:_(s32) = G_ANYEXT %4		%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5		$vgpr0 = COPY %5
...		...

		---
		name: test_ashr_v2s32_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_ashr_v2s32_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV2]](s32)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
		; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		; VI-LABEL: name: test_ashr_v2s32_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV2]](s32)
		; VI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
		; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		; GFX9-LABEL: name: test_ashr_v2s32_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV2]](s32)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
		; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
		%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
		%2:_(<2 x s32>) = G_ASHR %0, %1
		$vgpr0_vgpr1 = COPY %2
		...

		---
		name: test_ashr_v3s32_v3s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5

		; SI-LABEL: name: test_ashr_v3s32_v3s32
		; SI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV3]](s32)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV4]](s32)
		; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[UV5]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
		; SI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		; VI-LABEL: name: test_ashr_v3s32_v3s32
		; VI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV3]](s32)
		; VI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV4]](s32)
		; VI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[UV5]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
		; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		; GFX9-LABEL: name: test_ashr_v3s32_v3s32
		; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV]], [[UV3]](s32)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[UV4]](s32)
		; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[UV5]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
		; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		%2:_(<3 x s32>) = G_ASHR %0, %1
		$vgpr0_vgpr1_vgpr2 = COPY %2
		...

		---
		name: test_ashr_v2s64_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5

		; SI-LABEL: name: test_ashr_v2s64_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV2]](s32)
		; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
		; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		; VI-LABEL: name: test_ashr_v2s64_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV2]](s32)
		; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
		; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		; GFX9-LABEL: name: test_ashr_v2s64_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV2]](s32)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64)
		; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
		%2:_(<2 x s64>) = G_ASHR %0, %1
		$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
		...

		---
		name: test_ashr_v3s64_v3s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10

		; SI-LABEL: name: test_ashr_v3s64_v3s32
		; SI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV3]](s32)
		; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV4]](s32)
		; SI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV2]], [[UV5]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64), [[ASHR2]](s64)
		; SI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; SI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		; VI-LABEL: name: test_ashr_v3s64_v3s32
		; VI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV3]](s32)
		; VI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV4]](s32)
		; VI: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV2]], [[UV5]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64), [[ASHR2]](s64)
		; VI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; VI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		; GFX9-LABEL: name: test_ashr_v3s64_v3s32
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV]], [[UV3]](s32)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[UV4]](s32)
		; GFX9: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV2]], [[UV5]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ASHR]](s64), [[ASHR1]](s64), [[ASHR2]](s64)
		; GFX9: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<3 x s64>) = G_EXTRACT %0, 0
		%2:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		%3:_(<3 x s64>) = G_ASHR %1, %2
		%4:_(<4 x s64>) = G_IMPLICIT_DEF
		%5:_(<4 x s64>) = G_INSERT %4, %3, 0
		$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
		...

		---
		name: test_ashr_v2s16_v2s16
		body: \|
		bb.0:
		liveins: $vgpr0, $vgpr1

		; SI-LABEL: name: test_ashr_v2s16_v2s16
		; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; SI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
		; SI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
		; SI: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT1]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; VI-LABEL: name: test_ashr_v2s16_v2s16
		; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; VI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[UV]], [[UV2]](s16)
		; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[UV1]], [[UV3]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16)
		; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; GFX9-LABEL: name: test_ashr_v2s16_v2s16
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
		; GFX9: $vgpr0 = COPY [[ASHR]](<2 x s16>)
		%0:_(<2 x s16>) = COPY $vgpr0
		%1:_(<2 x s16>) = COPY $vgpr1
		%2:_(<2 x s16>) = G_ASHR %0, %1
		$vgpr0 = COPY %2
		...

		---
		name: test_ashr_v2s16_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0, $vgpr0_vgpr1

		; SI-LABEL: name: test_ashr_v2s16_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[UV2]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
		; SI: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[UV3]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; VI-LABEL: name: test_ashr_v2s16_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[UV]], [[UV2]](s32)
		; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16)
		; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; GFX9-LABEL: name: test_ashr_v2s16_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; GFX9: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[UV]], [[UV2]](s32)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16)
		; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		%0:_(<2 x s16>) = COPY $vgpr0
		%1:_(<2 x s32>) = COPY $vgpr0_vgpr1
		%2:_(<2 x s16>) = G_ASHR %0, %1
		$vgpr0 = COPY %2
		...

		---
		name: test_ashr_v3s16_v3s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_ashr_v3s16_v3s16
		; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; SI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
		; SI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
		; SI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
		; SI: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT1]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
		; SI: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
		; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
		; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT2]], [[ZEXT2]](s32)
		; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)
		; SI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; SI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
		; SI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
		; VI-LABEL: name: test_ashr_v3s16_v3s16
		; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; VI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
		; VI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[UV]], [[UV3]](s16)
		; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[UV1]], [[UV4]](s16)
		; VI: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[UV2]], [[UV5]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16), [[ASHR2]](s16)
		; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; VI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
		; VI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
		; GFX9-LABEL: name: test_ashr_v3s16_v3s16
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; GFX9: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT]](<3 x s16>), 0
		; GFX9: [[EXTRACT3:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT]](<3 x s16>), 32
		; GFX9: [[EXTRACT4:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 0
		; GFX9: [[EXTRACT5:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 32
		; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[EXTRACT2]], [[EXTRACT4]](<2 x s16>)
		; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[EXTRACT3]], [[EXTRACT5]](s16)
		; GFX9: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[DEF]], [[ASHR]](<2 x s16>), 0
		; GFX9: [[INSERT1:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[INSERT]], [[ASHR1]](s16), 32
		; GFX9: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[INSERT1]](<3 x s16>), 0
		; GFX9: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
		%2:_(<3 x s16>) = G_EXTRACT %0, 0
		%3:_(<3 x s16>) = G_EXTRACT %1, 0
		%4:_(<3 x s16>) = G_ASHR %2, %3
		%5:_(<4 x s16>) = G_IMPLICIT_DEF
		%6:_(<4 x s16>) = G_INSERT %5, %4, 0
		$vgpr0_vgpr1 = COPY %6
		...

		---
		name: test_ashr_v4s16_v4s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_ashr_v4s16_v4s16
		; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; SI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; SI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s16)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
		; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
		; SI: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
		; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT1]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
		; SI: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
		; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s16)
		; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT2]], [[ZEXT2]](s32)
		; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR2]](s32)
		; SI: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[UV3]](s16)
		; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s16)
		; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT3]], [[ZEXT3]](s32)
		; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
		; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
		; VI-LABEL: name: test_ashr_v4s16_v4s16
		; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; VI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[UV]], [[UV4]](s16)
		; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[UV1]], [[UV5]](s16)
		; VI: [[ASHR2:%[0-9]+]]:_(s16) = G_ASHR [[UV2]], [[UV6]](s16)
		; VI: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[UV3]], [[UV7]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ASHR]](s16), [[ASHR1]](s16), [[ASHR2]](s16), [[ASHR3]](s16)
		; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
		; GFX9-LABEL: name: test_ashr_v4s16_v4s16
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[UV]], [[UV2]](<2 x s16>)
		; GFX9: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[UV1]], [[UV3]](<2 x s16>)
		; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ASHR]](<2 x s16>), [[ASHR1]](<2 x s16>)
		; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
		%2:_(<4 x s16>) = G_ASHR %0, %1
		$vgpr0_vgpr1 = COPY %2
		...

test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: test_lshr_i32_i32		name: test_lshr_s32_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_lshr_i32_i32		; SI-LABEL: name: test_lshr_s32_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; SI: $vgpr0 = COPY [[LSHR]](s32)		; SI: $vgpr0 = COPY [[LSHR]](s32)
; VI-LABEL: name: test_lshr_i32_i32		; VI-LABEL: name: test_lshr_s32_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; VI: $vgpr0 = COPY [[LSHR]](s32)		; VI: $vgpr0 = COPY [[LSHR]](s32)
; GFX9-LABEL: name: test_lshr_i32_i32		; GFX9-LABEL: name: test_lshr_s32_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
; GFX9: $vgpr0 = COPY [[LSHR]](s32)		; GFX9: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_LSHR %0, %1		%2:_(s32) = G_LSHR %0, %1
$vgpr0 = COPY %2		$vgpr0 = COPY %2
...		...
---		---
name: test_lshr_i64_i64		name: test_lshr_s64_s64
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

; SI-LABEL: name: test_lshr_i64_i64		; SI-LABEL: name: test_lshr_s64_s64
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; VI-LABEL: name: test_lshr_i64_i64		; VI-LABEL: name: test_lshr_s64_s64
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; GFX9-LABEL: name: test_lshr_i64_i64		; GFX9-LABEL: name: test_lshr_s64_s64
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3		; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)		; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3		%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_LSHR %0, %1		%2:_(s64) = G_LSHR %0, %1
$vgpr0_vgpr1 = COPY %2		$vgpr0_vgpr1 = COPY %2
...		...
---		---
name: test_lshr_i64_i32		name: test_lshr_s64_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2		liveins: $vgpr0_vgpr1, $vgpr2

; SI-LABEL: name: test_lshr_i64_i32		; SI-LABEL: name: test_lshr_s64_s32
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; VI-LABEL: name: test_lshr_i64_i32		; VI-LABEL: name: test_lshr_s64_s32
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; GFX9-LABEL: name: test_lshr_i64_i32		; GFX9-LABEL: name: test_lshr_s64_s32
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2		%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_LSHR %0, %1		%2:_(s64) = G_LSHR %0, %1
$vgpr0_vgpr1 = COPY %2		$vgpr0_vgpr1 = COPY %2
...		...
---		---
name: test_lshr_i64_i16		name: test_lshr_s64_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2		liveins: $vgpr0_vgpr1, $vgpr2

; SI-LABEL: name: test_lshr_i64_i16		; SI-LABEL: name: test_lshr_s64_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; VI-LABEL: name: test_lshr_i64_i16		; VI-LABEL: name: test_lshr_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; GFX9-LABEL: name: test_lshr_i64_i16		; GFX9-LABEL: name: test_lshr_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1		; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)		; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1		%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2		%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1		%2:_(s16) = G_TRUNC %1
%3:_(s64) = G_LSHR %0, %2		%3:_(s64) = G_LSHR %0, %2
$vgpr0_vgpr1 = COPY %3		$vgpr0_vgpr1 = COPY %3
...		...

---		---
name: test_lshr_i16_i32		name: test_lshr_s16_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_lshr_i16_i32		; SI-LABEL: name: test_lshr_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY3]](s32)		; SI: $vgpr0 = COPY [[COPY3]](s32)
; VI-LABEL: name: test_lshr_i16_i32		; VI-LABEL: name: test_lshr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i16_i32		; GFX9-LABEL: name: test_lshr_s16_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0		%2:_(s16) = G_TRUNC %0
%3:_(s16) = G_LSHR %2, %1		%3:_(s16) = G_LSHR %2, %1
%4:_(s32) = G_ANYEXT %3		%4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4		$vgpr0 = COPY %4
...		...

---		---
name: test_lshr_i16_i16		name: test_lshr_s16_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_lshr_i16_i16		; SI-LABEL: name: test_lshr_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]		; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)		; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_i16_i16		; VI-LABEL: name: test_lshr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i16_i16		; GFX9-LABEL: name: test_lshr_s16_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)		; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0		%2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1		%3:_(s16) = G_TRUNC %1
%4:_(s16) = G_LSHR %2, %3		%4:_(s16) = G_LSHR %2, %3
%5:_(s32) = G_ANYEXT %4		%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5		$vgpr0 = COPY %5
...		...

---		---
name: test_lshr_i16_i8		name: test_lshr_s16_i8
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; SI-LABEL: name: test_lshr_i16_i8		; SI-LABEL: name: test_lshr_s16_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]		; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)		; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_i16_i8		; VI-LABEL: name: test_lshr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)		; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i16_i8		; GFX9-LABEL: name: test_lshr_s16_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]		; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)		; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)		; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	bb.0:
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0		%2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1		%3:_(s8) = G_TRUNC %1
%4:_(s8) = G_LSHR %2, %3		%4:_(s8) = G_LSHR %2, %3
%5:_(s32) = G_ANYEXT %4		%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5		$vgpr0 = COPY %5
...		...

		---
		name: test_lshr_v2s32_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_lshr_v2s32_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV2]](s32)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
		; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		; VI-LABEL: name: test_lshr_v2s32_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV2]](s32)
		; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
		; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		; GFX9-LABEL: name: test_lshr_v2s32_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
		; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV2]](s32)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32)
		; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
		%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
		%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
		%2:_(<2 x s32>) = G_LSHR %0, %1
		$vgpr0_vgpr1 = COPY %2
		...

		---
		name: test_lshr_v3s32_v3s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5

		; SI-LABEL: name: test_lshr_v3s32_v3s32
		; SI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV3]](s32)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV4]](s32)
		; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[UV5]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
		; SI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		; VI-LABEL: name: test_lshr_v3s32_v3s32
		; VI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV3]](s32)
		; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV4]](s32)
		; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[UV5]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
		; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		; GFX9-LABEL: name: test_lshr_v3s32_v3s32
		; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
		; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[UV3]](s32)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[UV4]](s32)
		; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[UV5]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
		; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
		%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
		%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
		%2:_(<3 x s32>) = G_LSHR %0, %1
		$vgpr0_vgpr1_vgpr2 = COPY %2
		...

		---
		name: test_lshr_v2s64_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5

		; SI-LABEL: name: test_lshr_v2s64_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV2]](s32)
		; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64)
		; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		; VI-LABEL: name: test_lshr_v2s64_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV2]](s32)
		; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64)
		; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		; GFX9-LABEL: name: test_lshr_v2s64_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
		; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV2]](s32)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64)
		; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
		%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
		%2:_(<2 x s64>) = G_LSHR %0, %1
		$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
		...

		---
		name: test_lshr_v3s64_v3s32
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10

		; SI-LABEL: name: test_lshr_v3s64_v3s32
		; SI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV3]](s32)
		; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV4]](s32)
		; SI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[UV5]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64), [[LSHR2]](s64)
		; SI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; SI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		; VI-LABEL: name: test_lshr_v3s64_v3s32
		; VI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV3]](s32)
		; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV4]](s32)
		; VI: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[UV5]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64), [[LSHR2]](s64)
		; VI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; VI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		; GFX9-LABEL: name: test_lshr_v3s64_v3s32
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
		; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
		; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
		; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[UV]], [[UV3]](s32)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[UV1]], [[UV4]](s32)
		; GFX9: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[UV2]], [[UV5]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[LSHR]](s64), [[LSHR1]](s64), [[LSHR2]](s64)
		; GFX9: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
		; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
		%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
		%1:_(<3 x s64>) = G_EXTRACT %0, 0
		%2:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
		%3:_(<3 x s64>) = G_LSHR %1, %2
		%4:_(<4 x s64>) = G_IMPLICIT_DEF
		%5:_(<4 x s64>) = G_INSERT %4, %3, 0
		$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
		...

		---
		name: test_lshr_v2s16_v2s16
		body: \|
		bb.0:
		liveins: $vgpr0, $vgpr1

		; SI-LABEL: name: test_lshr_v2s16_v2s16
		; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; SI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT1]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
		; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
		; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT2]], [[ZEXT3]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; VI-LABEL: name: test_lshr_v2s16_v2s16
		; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; VI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UV]], [[UV2]](s16)
		; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[UV1]], [[UV3]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LSHR]](s16), [[LSHR1]](s16)
		; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; GFX9-LABEL: name: test_lshr_v2s16_v2s16
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
		; GFX9: [[LSHR:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>)
		; GFX9: $vgpr0 = COPY [[LSHR]](<2 x s16>)
		%0:_(<2 x s16>) = COPY $vgpr0
		%1:_(<2 x s16>) = COPY $vgpr1
		%2:_(<2 x s16>) = G_LSHR %0, %1
		$vgpr0 = COPY %2
		...

		---
		name: test_lshr_v2s16_v2s32
		body: \|
		bb.0:
		liveins: $vgpr0, $vgpr0_vgpr1

		; SI-LABEL: name: test_lshr_v2s16_v2s32
		; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[UV2]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT1]], [[UV3]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; VI-LABEL: name: test_lshr_v2s16_v2s32
		; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UV]], [[UV2]](s32)
		; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[UV1]], [[UV3]](s32)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LSHR]](s16), [[LSHR1]](s16)
		; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		; GFX9-LABEL: name: test_lshr_v2s16_v2s32
		; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
		; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
		; GFX9: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
		; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
		; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UV]], [[UV2]](s32)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[UV1]], [[UV3]](s32)
		; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LSHR]](s16), [[LSHR1]](s16)
		; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		%0:_(<2 x s16>) = COPY $vgpr0
		%1:_(<2 x s32>) = COPY $vgpr0_vgpr1
		%2:_(<2 x s16>) = G_LSHR %0, %1
		$vgpr0 = COPY %2
		...

		---
		name: test_lshr_v3s16_v3s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_lshr_v3s16_v3s16
		; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; SI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
		; SI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT1]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
		; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
		; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT2]], [[ZEXT3]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
		; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
		; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
		; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT4]], [[ZEXT5]](s32)
		; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)
		; SI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; SI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
		; SI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
		; VI-LABEL: name: test_lshr_v3s16_v3s16
		; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; VI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
		; VI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UV]], [[UV3]](s16)
		; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[UV1]], [[UV4]](s16)
		; VI: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[UV2]], [[UV5]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[LSHR]](s16), [[LSHR1]](s16), [[LSHR2]](s16)
		; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; VI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
		; VI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
		; GFX9-LABEL: name: test_lshr_v3s16_v3s16
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
		; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
		; GFX9: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT]](<3 x s16>), 0
		; GFX9: [[EXTRACT3:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT]](<3 x s16>), 32
		; GFX9: [[EXTRACT4:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 0
		; GFX9: [[EXTRACT5:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 32
		; GFX9: [[LSHR:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[EXTRACT2]], [[EXTRACT4]](<2 x s16>)
		; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[EXTRACT3]], [[EXTRACT5]](s16)
		; GFX9: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[DEF]], [[LSHR]](<2 x s16>), 0
		; GFX9: [[INSERT1:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[INSERT]], [[LSHR1]](s16), 32
		; GFX9: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
		; GFX9: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[INSERT1]](<3 x s16>), 0
		; GFX9: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
		%2:_(<3 x s16>) = G_EXTRACT %0, 0
		%3:_(<3 x s16>) = G_EXTRACT %1, 0
		%4:_(<3 x s16>) = G_LSHR %2, %3
		%5:_(<4 x s16>) = G_IMPLICIT_DEF
		%6:_(<4 x s16>) = G_INSERT %5, %4, 0
		$vgpr0_vgpr1 = COPY %6
		...

		---
		name: test_lshr_v4s16_v4s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

		; SI-LABEL: name: test_lshr_v4s16_v4s16
		; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; SI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
		; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
		; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT1]](s32)
		; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
		; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
		; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
		; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT2]], [[ZEXT3]](s32)
		; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
		; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
		; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s16)
		; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT4]], [[ZEXT5]](s32)
		; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
		; SI: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
		; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s16)
		; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT6]], [[ZEXT7]](s32)
		; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
		; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
		; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
		; VI-LABEL: name: test_lshr_v4s16_v4s16
		; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; VI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UV]], [[UV4]](s16)
		; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[UV1]], [[UV5]](s16)
		; VI: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[UV2]], [[UV6]](s16)
		; VI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[UV3]], [[UV7]](s16)
		; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[LSHR]](s16), [[LSHR1]](s16), [[LSHR2]](s16), [[LSHR3]](s16)
		; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
		; GFX9-LABEL: name: test_lshr_v4s16_v4s16
		; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
		; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
		; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
		; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
		; GFX9: [[LSHR:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[UV]], [[UV2]](<2 x s16>)
		; GFX9: [[LSHR1:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[UV1]], [[UV3]](<2 x s16>)
		; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[LSHR]](<2 x s16>), [[LSHR1]](<2 x s16>)
		; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
		%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
		%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
		%2:_(<4 x s16>) = G_LSHR %0, %1
		$vgpr0_vgpr1 = COPY %2
		...

test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s			# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=SI %s
	# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s			# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=VI %s
	# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s			# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

	---			---
	name: test_shl_i32_i32			name: test_shl_s32_s32
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1

	; CHECK-LABEL: name: test_shl_i32_i32			; SI-LABEL: name: test_shl_s32_s32
	; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
	; CHECK: $vgpr0 = COPY [[SHL]](s32)
	; SI-LABEL: name: test_shl_i32_i32
	; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)			; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
	; SI: $vgpr0 = COPY [[SHL]](s32)			; SI: $vgpr0 = COPY [[SHL]](s32)
	; VI-LABEL: name: test_shl_i32_i32			; VI-LABEL: name: test_shl_s32_s32
	; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)			; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
	; VI: $vgpr0 = COPY [[SHL]](s32)			; VI: $vgpr0 = COPY [[SHL]](s32)
	; GFX9-LABEL: name: test_shl_i32_i32			; GFX9-LABEL: name: test_shl_s32_s32
	; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
	; GFX9: $vgpr0 = COPY [[SHL]](s32)			; GFX9: $vgpr0 = COPY [[SHL]](s32)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32) = G_SHL %0, %1			%2:_(s32) = G_SHL %0, %1
	$vgpr0 = COPY %2			$vgpr0 = COPY %2
	...			...
	---			---
	name: test_shl_i64_i64			name: test_shl_s64_s64
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2_vgpr3			liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

	; CHECK-LABEL: name: test_shl_i64_i64			; SI-LABEL: name: test_shl_s64_s64
	; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
	; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
	; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
	; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; SI-LABEL: name: test_shl_i64_i64
	; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3			; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
	; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)			; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
	; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)			; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
	; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; VI-LABEL: name: test_shl_i64_i64			; VI-LABEL: name: test_shl_s64_s64
	; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3			; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
	; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)			; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
	; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)			; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
	; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; GFX9-LABEL: name: test_shl_i64_i64			; GFX9-LABEL: name: test_shl_s64_s64
	; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3			; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
	; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)			; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
	; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
	; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	%0:_(s64) = COPY $vgpr0_vgpr1			%0:_(s64) = COPY $vgpr0_vgpr1
	%1:_(s64) = COPY $vgpr2_vgpr3			%1:_(s64) = COPY $vgpr2_vgpr3
	%2:_(s64) = G_SHL %0, %1			%2:_(s64) = G_SHL %0, %1
	$vgpr0_vgpr1 = COPY %2			$vgpr0_vgpr1 = COPY %2
	...			...
	---			---
	name: test_shl_i64_i32			name: test_shl_s64_s32
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2			liveins: $vgpr0_vgpr1, $vgpr2

	; CHECK-LABEL: name: test_shl_i64_i32			; SI-LABEL: name: test_shl_s64_s32
	; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
	; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; SI-LABEL: name: test_shl_i64_i32
	; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)			; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
	; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; VI-LABEL: name: test_shl_i64_i32			; VI-LABEL: name: test_shl_s64_s32
	; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)			; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
	; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; GFX9-LABEL: name: test_shl_i64_i32			; GFX9-LABEL: name: test_shl_s64_s32
	; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
	; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	%0:_(s64) = COPY $vgpr0_vgpr1			%0:_(s64) = COPY $vgpr0_vgpr1
	%1:_(s32) = COPY $vgpr2			%1:_(s32) = COPY $vgpr2
	%2:_(s64) = G_SHL %0, %1			%2:_(s64) = G_SHL %0, %1
	$vgpr0_vgpr1 = COPY %2			$vgpr0_vgpr1 = COPY %2
	...			...
	---			---
	name: test_shl_i64_i16			name: test_shl_s64_s16
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2			liveins: $vgpr0_vgpr1, $vgpr2

	; CHECK-LABEL: name: test_shl_i64_i16			; SI-LABEL: name: test_shl_s64_s16
	; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
	; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; SI-LABEL: name: test_shl_i64_i16
	; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535			; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]			; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)			; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
	; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; VI-LABEL: name: test_shl_i64_i16			; VI-LABEL: name: test_shl_s64_s16
	; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535			; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]			; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)			; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
	; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	; GFX9-LABEL: name: test_shl_i64_i16			; GFX9-LABEL: name: test_shl_s64_s16
	; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1			; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
	; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535			; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]			; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
	; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)			; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
	%0:_(s64) = COPY $vgpr0_vgpr1			%0:_(s64) = COPY $vgpr0_vgpr1
	%1:_(s32) = COPY $vgpr2			%1:_(s32) = COPY $vgpr2
	%2:_(s16) = G_TRUNC %1			%2:_(s16) = G_TRUNC %1
	%3:_(s64) = G_SHL %0, %2			%3:_(s64) = G_SHL %0, %2
	$vgpr0_vgpr1 = COPY %3			$vgpr0_vgpr1 = COPY %3
	...			...

	---			---
	name: test_shl_i16_i32			name: test_shl_s16_s32
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1

	; SI-LABEL: name: test_shl_i16_i32			; SI-LABEL: name: test_shl_s16_s32
	; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)			; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
	; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)			; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
	; SI: $vgpr0 = COPY [[COPY3]](s32)			; SI: $vgpr0 = COPY [[COPY3]](s32)
	; VI-LABEL: name: test_shl_i16_i32			; VI-LABEL: name: test_shl_s16_s32
	; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)			; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
	; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; VI: $vgpr0 = COPY [[ANYEXT]](s32)			; VI: $vgpr0 = COPY [[ANYEXT]](s32)
	; GFX9-LABEL: name: test_shl_i16_i32			; GFX9-LABEL: name: test_shl_s16_s32
	; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
	; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)			; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s16) = G_SHL %2, %1			%3:_(s16) = G_SHL %2, %1
	%4:_(s32) = G_ANYEXT %3			%4:_(s32) = G_ANYEXT %3
	$vgpr0 = COPY %4			$vgpr0 = COPY %4
	...			...

	---			---
	name: test_shl_i16_i16			name: test_shl_s16_s16
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1

	; SI-LABEL: name: test_shl_i16_i16			; SI-LABEL: name: test_shl_s16_s16
	; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535			; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
	; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]			; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
	; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)			; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
	; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)			; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
	; SI: $vgpr0 = COPY [[COPY4]](s32)			; SI: $vgpr0 = COPY [[COPY4]](s32)
	; VI-LABEL: name: test_shl_i16_i16			; VI-LABEL: name: test_shl_s16_s16
	; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)			; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
	; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)			; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
	; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; VI: $vgpr0 = COPY [[ANYEXT]](s32)			; VI: $vgpr0 = COPY [[ANYEXT]](s32)
	; GFX9-LABEL: name: test_shl_i16_i16			; GFX9-LABEL: name: test_shl_s16_s16
	; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)			; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
	; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)			; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
	; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)			; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s16) = G_TRUNC %1			%3:_(s16) = G_TRUNC %1
	%4:_(s16) = G_SHL %2, %3			%4:_(s16) = G_SHL %2, %3
	%5:_(s32) = G_ANYEXT %4			%5:_(s32) = G_ANYEXT %4
	$vgpr0 = COPY %5			$vgpr0 = COPY %5
	...			...

	---			---
	name: test_shl_i16_i8			name: test_shl_s16_i8
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1

	; SI-LABEL: name: test_shl_i16_i8			; SI-LABEL: name: test_shl_s16_i8
	; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255			; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]			; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
	; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)			; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
	; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)			; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
	; SI: $vgpr0 = COPY [[COPY4]](s32)			; SI: $vgpr0 = COPY [[COPY4]](s32)
	; VI-LABEL: name: test_shl_i16_i8			; VI-LABEL: name: test_shl_s16_i8
	; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255			; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]			; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)			; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
	; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; VI: $vgpr0 = COPY [[ANYEXT]](s32)			; VI: $vgpr0 = COPY [[ANYEXT]](s32)
	; GFX9-LABEL: name: test_shl_i16_i8			; GFX9-LABEL: name: test_shl_s16_i8
	; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0			; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
	; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1			; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
	; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)			; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
	; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255			; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
	; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]			; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
	; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)			; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
	; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)			; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
	; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)			; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s8) = G_TRUNC %1			%3:_(s8) = G_TRUNC %1
	%4:_(s16) = G_SHL %2, %3			%4:_(s16) = G_SHL %2, %3
	%5:_(s32) = G_ANYEXT %4			%5:_(s32) = G_ANYEXT %4
	$vgpr0 = COPY %5			$vgpr0 = COPY %5
	...			...

	---			---
	name: test_shl_i8_i8			name: test_shl_i8_i8
	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1

				; SI-LABEL: name: test_shl_i8_i8
				; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
				; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
				; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
				; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
				; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
				; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
				; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
				; SI: $vgpr0 = COPY [[COPY4]](s32)
				; VI-LABEL: name: test_shl_i8_i8
				; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
				; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
				; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
				; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
				; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
				; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
				; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
				; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
				; VI: $vgpr0 = COPY [[ANYEXT]](s32)
				; GFX9-LABEL: name: test_shl_i8_i8
				; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
				; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
				; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
				; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
				; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
				; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
				; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
				; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
				; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s8) = G_TRUNC %0			%2:_(s8) = G_TRUNC %0
	%3:_(s8) = G_TRUNC %1			%3:_(s8) = G_TRUNC %1
	%4:_(s8) = G_SHL %2, %3			%4:_(s8) = G_SHL %2, %3
	%5:_(s32) = G_ANYEXT %4			%5:_(s32) = G_ANYEXT %4
	$vgpr0 = COPY %5			$vgpr0 = COPY %5
	...			...

				---
				name: test_shl_v2s32_v2s32
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

				; SI-LABEL: name: test_shl_v2s32_v2s32
				; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
				; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
				; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV2]](s32)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV3]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32)
				; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
				; VI-LABEL: name: test_shl_v2s32_v2s32
				; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
				; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
				; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV2]](s32)
				; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV3]](s32)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32)
				; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
				; GFX9-LABEL: name: test_shl_v2s32_v2s32
				; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
				; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
				; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV2]](s32)
				; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV3]](s32)
				; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32)
				; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
				%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
				%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
				%2:_(<2 x s32>) = G_SHL %0, %1
				$vgpr0_vgpr1 = COPY %2
				...

				---
				name: test_shl_v3s32_v3s32
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5

				; SI-LABEL: name: test_shl_v3s32_v3s32
				; SI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
				; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
				; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
				; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV3]](s32)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV4]](s32)
				; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[UV5]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32), [[SHL2]](s32)
				; SI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
				; VI-LABEL: name: test_shl_v3s32_v3s32
				; VI: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
				; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
				; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
				; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV3]](s32)
				; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV4]](s32)
				; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[UV5]](s32)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32), [[SHL2]](s32)
				; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
				; GFX9-LABEL: name: test_shl_v3s32_v3s32
				; GFX9: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
				; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
				; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
				; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[UV3]](s32)
				; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[UV1]], [[UV4]](s32)
				; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[UV2]], [[UV5]](s32)
				; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SHL]](s32), [[SHL1]](s32), [[SHL2]](s32)
				; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
				%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
				%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
				%2:_(<3 x s32>) = G_SHL %0, %1
				$vgpr0_vgpr1_vgpr2 = COPY %2
				...

				---
				name: test_shl_v2s64_v2s32
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5

				; SI-LABEL: name: test_shl_v2s64_v2s32
				; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
				; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
				; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
				; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV2]](s32)
				; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV3]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64)
				; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
				; VI-LABEL: name: test_shl_v2s64_v2s32
				; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
				; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
				; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
				; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV2]](s32)
				; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV3]](s32)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64)
				; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
				; GFX9-LABEL: name: test_shl_v2s64_v2s32
				; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
				; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr4_vgpr5
				; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
				; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV2]](s32)
				; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV3]](s32)
				; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64)
				; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
				%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
				%1:_(<2 x s32>) = COPY $vgpr4_vgpr5
				%2:_(<2 x s64>) = G_SHL %0, %1
				$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
				...

				---
				name: test_shl_v3s64_v3s32
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10

				; SI-LABEL: name: test_shl_v3s64_v3s32
				; SI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
				; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
				; SI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
				; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
				; SI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV3]](s32)
				; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV4]](s32)
				; SI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[UV5]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64), [[SHL2]](s64)
				; SI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
				; SI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
				; SI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
				; VI-LABEL: name: test_shl_v3s64_v3s32
				; VI: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
				; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
				; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
				; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
				; VI: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV3]](s32)
				; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV4]](s32)
				; VI: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[UV5]](s32)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64), [[SHL2]](s64)
				; VI: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
				; VI: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
				; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
				; GFX9-LABEL: name: test_shl_v3s64_v3s32
				; GFX9: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
				; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
				; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
				; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
				; GFX9: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
				; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[UV]], [[UV3]](s32)
				; GFX9: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[UV1]], [[UV4]](s32)
				; GFX9: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[UV2]], [[UV5]](s32)
				; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SHL]](s64), [[SHL1]](s64), [[SHL2]](s64)
				; GFX9: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
				; GFX9: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s64>), 0
				; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
				%0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
				%1:_(<3 x s64>) = G_EXTRACT %0, 0
				%2:_(<3 x s32>) = COPY $vgpr8_vgpr9_vgpr10
				%3:_(<3 x s64>) = G_SHL %1, %2
				%4:_(<4 x s64>) = G_IMPLICIT_DEF
				%5:_(<4 x s64>) = G_INSERT %4, %3, 0
				$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
				...

				---
				name: test_shl_v2s16_v2s16
				body: \|
				bb.0:
				liveins: $vgpr0, $vgpr1

				; SI-LABEL: name: test_shl_v2s16_v2s16
				; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
				; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
				; SI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
				; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
				; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT]](s32)
				; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
				; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
				; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT1]](s32)
				; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
				; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
				; VI-LABEL: name: test_shl_v2s16_v2s16
				; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
				; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
				; VI: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
				; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[UV]], [[UV2]](s16)
				; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[UV1]], [[UV3]](s16)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SHL]](s16), [[SHL1]](s16)
				; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
				; GFX9-LABEL: name: test_shl_v2s16_v2s16
				; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
				; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
				; GFX9: $vgpr0 = COPY [[SHL]](<2 x s16>)
				%0:_(<2 x s16>) = COPY $vgpr0
				%1:_(<2 x s16>) = COPY $vgpr1
				%2:_(<2 x s16>) = G_SHL %0, %1
				$vgpr0 = COPY %2
				...

				---
				name: test_shl_v2s16_v2s32
				body: \|
				bb.0:
				liveins: $vgpr0, $vgpr0_vgpr1

				; SI-LABEL: name: test_shl_v2s16_v2s32
				; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
				; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[UV2]](s32)
				; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
				; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[UV3]](s32)
				; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
				; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
				; VI-LABEL: name: test_shl_v2s16_v2s32
				; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
				; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[UV]], [[UV2]](s32)
				; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[UV1]], [[UV3]](s32)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SHL]](s16), [[SHL1]](s16)
				; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
				; GFX9-LABEL: name: test_shl_v2s16_v2s32
				; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
				; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
				; GFX9: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
				; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
				; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[UV]], [[UV2]](s32)
				; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[UV1]], [[UV3]](s32)
				; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[SHL]](s16), [[SHL1]](s16)
				; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
				%0:_(<2 x s16>) = COPY $vgpr0
				%1:_(<2 x s32>) = COPY $vgpr0_vgpr1
				%2:_(<2 x s16>) = G_SHL %0, %1
				$vgpr0 = COPY %2
				...

				---
				name: test_shl_v3s16_v3s16
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

				; SI-LABEL: name: test_shl_v3s16_v3s16
				; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
				; SI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
				; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
				; SI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
				; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
				; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT]](s32)
				; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
				; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
				; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT1]](s32)
				; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
				; SI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
				; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
				; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT2]](s32)
				; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)
				; SI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
				; SI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
				; SI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
				; VI-LABEL: name: test_shl_v3s16_v3s16
				; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
				; VI: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
				; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
				; VI: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
				; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[UV]], [[UV3]](s16)
				; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[UV1]], [[UV4]](s16)
				; VI: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[UV2]], [[UV5]](s16)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[SHL]](s16), [[SHL1]](s16), [[SHL2]](s16)
				; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
				; VI: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[BUILD_VECTOR]](<3 x s16>), 0
				; VI: $vgpr0_vgpr1 = COPY [[INSERT]](<4 x s16>)
				; GFX9-LABEL: name: test_shl_v3s16_v3s16
				; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
				; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY1]](<4 x s16>), 0
				; GFX9: [[EXTRACT2:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT]](<3 x s16>), 0
				; GFX9: [[EXTRACT3:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT]](<3 x s16>), 32
				; GFX9: [[EXTRACT4:%[0-9]+]]:_(<2 x s16>) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 0
				; GFX9: [[EXTRACT5:%[0-9]+]]:_(s16) = G_EXTRACT [[EXTRACT1]](<3 x s16>), 32
				; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[EXTRACT2]], [[EXTRACT4]](<2 x s16>)
				; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[EXTRACT3]], [[EXTRACT5]](s16)
				; GFX9: [[DEF:%[0-9]+]]:_(<3 x s16>) = G_IMPLICIT_DEF
				; GFX9: [[INSERT:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[DEF]], [[SHL]](<2 x s16>), 0
				; GFX9: [[INSERT1:%[0-9]+]]:_(<3 x s16>) = G_INSERT [[INSERT]], [[SHL1]](s16), 32
				; GFX9: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
				; GFX9: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[INSERT1]](<3 x s16>), 0
				; GFX9: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
				%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
				%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
				%2:_(<3 x s16>) = G_EXTRACT %0, 0
				%3:_(<3 x s16>) = G_EXTRACT %1, 0
				%4:_(<3 x s16>) = G_SHL %2, %3
				%5:_(<4 x s16>) = G_IMPLICIT_DEF
				%6:_(<4 x s16>) = G_INSERT %5, %4, 0
				$vgpr0_vgpr1 = COPY %6
				...

				---
				name: test_shl_v4s16_v4s16
				body: \|
				bb.0:
				liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

				; SI-LABEL: name: test_shl_v4s16_v4s16
				; SI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; SI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; SI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
				; SI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
				; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
				; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV4]](s16)
				; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT]](s32)
				; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
				; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
				; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV5]](s16)
				; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT1]](s32)
				; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
				; SI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
				; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV6]](s16)
				; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT2]](s32)
				; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
				; SI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
				; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s16)
				; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT3]], [[ZEXT3]](s32)
				; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
				; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
				; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
				; VI-LABEL: name: test_shl_v4s16_v4s16
				; VI: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; VI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; VI: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
				; VI: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
				; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[UV]], [[UV4]](s16)
				; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[UV1]], [[UV5]](s16)
				; VI: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[UV2]], [[UV6]](s16)
				; VI: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[UV3]], [[UV7]](s16)
				; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[SHL]](s16), [[SHL1]](s16), [[SHL2]](s16), [[SHL3]](s16)
				; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>)
				; GFX9-LABEL: name: test_shl_v4s16_v4s16
				; GFX9: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
				; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
				; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
				; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
				; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[UV]], [[UV2]](<2 x s16>)
				; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[UV1]], [[UV3]](<2 x s16>)
				; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SHL]](<2 x s16>), [[SHL1]](<2 x s16>)
				; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
				%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
				%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
				%2:_(<4 x s16>) = G_SHL %0, %1
				$vgpr0_vgpr1 = COPY %2
				...

This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Implement fewerElementsVector for shiftsClosedPublic

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Diff 185338

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

GlobalISel: Implement fewerElementsVector for shifts
ClosedPublic