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Differential D57471

[LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_elt
ClosedPublic

Authored by tlively on Jan 30 2019, 1:48 PM.

Details

Reviewers
aheejin
Commits
rG9510adafe6ab: [LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_elt
rL352702: [LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_elt
Summary

Fixes PR40267, in which the removed assertion was triggering on
perfectly valid IR. As far as I can tell, constant out of bounds
indices should be allowed when splitting extract_vector_elt, since
they will simply be propagated as out of bounds indices in the
resulting split vector and handled appropriately elsewhere.

Diff Detail

Event Timeline

tlively created this revision.Jan 30 2019, 1:48 PM
Herald added subscribers: hiraditya, jgravelle-google, sbc100, dschuff. · View Herald TranscriptJan 30 2019, 1:48 PM
Harbormaster completed remote builds in B27503: Diff 184360.Jan 30 2019, 1:49 PM
aheejin accepted this revision.Jan 30 2019, 4:02 PM
This revision is now accepted and ready to land.Jan 30 2019, 4:02 PM
Closed by commit rL352702: [LegalizeVectorTypes] Allow illegal indices when splitting extract_vector_elt (authored by tlively). · Explain WhyJan 30 2019, 4:36 PM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptJan 30 2019, 4:36 PM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
1 line
test/
CodeGen/
WebAssembly/
22 lines

Diff 184360

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Show First 20 Lines • Show All 1,913 Lines • ▼ Show 20 Lines
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue Vec = N->getOperand(0); SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1); SDValue Idx = N->getOperand(1);
EVT VecVT = Vec.getValueType(); EVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) { if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
SDValue Lo, Hi; SDValue Lo, Hi;
GetSplitVector(Vec, Lo, Hi); GetSplitVector(Vec, Lo, Hi);
uint64_t LoElts = Lo.getValueType().getVectorNumElements(); uint64_t LoElts = Lo.getValueType().getVectorNumElements();
if (IdxVal < LoElts) if (IdxVal < LoElts)
return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
▲ Show 20 Lines • Show All 2,594 Lines • Show Last 20 Lines

llvm/test/CodeGen/WebAssembly/PR40267.ll

  • This file was added.
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers
; Regression test for PR40267. Tests that invalid indices in
; extract_vector_elt can be handled when vectors ops are split. Notice
; that SIMD is not enabled for this test. Check only that llc does not
; crash, since it would previously trigger an assertion.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
define void @foo() {
%L6 = load i32, i32* undef
br label %BB1
BB1: ; preds = %BB1, %0
%bj = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> <i32 55, i32 21, i32 92, i32 68>, <4 x i32> <i32 51, i32 61, i32 62, i32 39>
%E1 = extractelement <4 x i32> %bj, i32 0
%E23 = extractelement <4 x i32> zeroinitializer, i32 %E1
%I33 = insertelement <4 x i32> undef, i32 %E23, i1 undef
store <4 x i32> %I33, <4 x i32>* undef
br label %BB1
}