[RISCV] Fix failure to parse parenthesized immediates

[lewis-revill]

Summary

Since the parser attempts to parse an operand as a register with parentheses before parsing it as an immediate, immediates in parentheses should not be parsed by parseRegister. However in the case where the immediate does not start with an identifier, the LParen is not unlexed and so the RParen causes an unexpected token error.

This patch adds the missing UnLex, and modifies the existing UnLex to not use a buffered token, as it should always be unlexing an LParen.

[jrtc27]

You should save the original AsmToken rather than reconstructing it, so as to retain the SMLoc, and Buf no longer needs to be at function scope. Also, I had some more exhaustive tests in mine; I think the important one is addi a1, a0, (1) to ensure that we can parse parenthesised immediate expressions when *not* part of a memory reference.

[lewis-revill]

In D57319#1373436, @jrtc27 wrote:

You should save the original AsmToken rather than reconstructing it, so as to retain the SMLoc, and Buf no longer needs to be at function scope. Also, I had some more exhaustive tests in mine; I think the important one is addi a1, a0, (1) to ensure that we can parse parenthesised immediate expressions when *not* part of a memory reference.

That sounds like a good approach. It really wasn't possible that LParen could ever be in the buffer given the way 'peekTokens' works.

[lewis-revill]

Save the token for the parsed LParen rather than reconstructing one. Add some more tests.

[lewis-revill]

Rebased patch after addition of matchRegisterNameHelper

[asb]

This looks good to me, thanks!

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1002 ↗

(On Diff #204521)

This (pre-existing) sentence is garbled and you might want to fix it as part of this patch.

llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
   getParser().Lex(); // Eat identifier token.
   return false;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
                                                    bool AllowParens) {
   SMLoc FirstS = getLoc();
   bool HadParens = false;
-  AsmToken Buf[2];
+  AsmToken LParen;
 
-  // If this a parenthesised register name is allowed, parse it atomically
+  // If this is an LParen and a parenthesised register name is allowed, parse it
+  // atomically.
   if (AllowParens && getLexer().is(AsmToken::LParen)) {
+    AsmToken Buf[2];
     size_t ReadCount = getLexer().peekTokens(Buf);
     if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) {
       HadParens = true;
+      LParen = getParser().getTok();
       getParser().Lex(); // Eat '('
     }
   }
 
   switch (getLexer().getKind()) {
   default:
+    if (HadParens)
+      getLexer().UnLex(LParen);
     return MatchOperand_NoMatch;
   case AsmToken::Identifier:
     StringRef Name = getLexer().getTok().getIdentifier();
     unsigned RegNo;
     matchRegisterNameHelper(isRV32E(), RegNo, Name);
 
     if (RegNo == 0) {
       if (HadParens)
-        getLexer().UnLex(Buf[0]);
+        getLexer().UnLex(LParen);
       return MatchOperand_NoMatch;
     }
     if (HadParens)
       Operands.push_back(RISCVOperand::createToken("(", FirstS, isRV64()));
     SMLoc S = getLoc();
     SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
     getLexer().Lex();
     Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));

llvm/trunk/test/MC/RISCV/rv32i-valid.s

 # CHECK-ASM: jal a0, a0
 # CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
 # CHECK-OBJ: jal a0, 0
 # CHECK-OBJ: R_RISCV_JAL a0
 jal a0, a0
 # CHECK-ASM-AND-OBJ: jal a0, 30
 # CHECK-ASM: encoding: [0x6f,0x05,0xe0,0x01]
 jal a0, CONST
+# CHECK-ASM-AND-OBJ: jal s0, 0
+# CHECK-ASM: encoding: [0x6f,0x04,0x00,0x00]
+jal s0, (0)
+# CHECK-ASM-AND-OBJ: jal s0, 156
+# CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09]
+jal s0, (0xff-99)
 
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
 jalr a0, a1, -2048
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
 jalr a0, a1, %lo(2048)
 # CHECK-ASM-AND-OBJ: jalr t2, t1, 2047

 # CHECK-ASM: lhu t3, %pcrel_lo(foo)(t3)
 # CHECK-ASM: encoding: [0x03,0x5e,0bAAAA1110,A]
 # CHECK-OBJ: lhu t3, 0(t3)
 # CHECK-OBJ: R_RISCV_PCREL_LO12
 lhu t3, %pcrel_lo(foo)(t3)
 # CHECK-ASM-AND-OBJ: lb t0, 30(t1)
 # CHECK-ASM: encoding: [0x83,0x02,0xe3,0x01]
 lb t0, CONST(t1)
+# CHECK-ASM-AND-OBJ: lb s0, 0(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0x04,0x00]
+lb s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: lb s0, 156(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0xc4,0x09]
+lb s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: sb a0, 2047(a2)
 # CHECK-ASM: encoding: [0xa3,0x0f,0xa6,0x7e]
 sb a0, 2047(a2)
 # CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
 # CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
 sh t3, -2048(t5)
 # CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
 # CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
 sh t3, %lo(2048)(t5)
 # CHECK-ASM-AND-OBJ: sw ra, 999(zero)
 # CHECK-ASM: encoding: [0xa3,0x23,0x10,0x3e]
 sw ra, 999(zero)
 # CHECK-ASM-AND-OBJ: sw a0, 30(t0)
 # CHECK-ASM: encoding: [0x23,0xaf,0xa2,0x00]
 sw a0, CONST(t0)
+# CHECK-ASM-AND-OBJ: sw s0, 0(s1)
+# CHECK-ASM: encoding: [0x23,0xa0,0x84,0x00]
+sw s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: sw s0, 156(s1)
+# CHECK-ASM: encoding: [0x23,0xae,0x84,0x08]
+sw s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: addi ra, sp, 2
 # CHECK-ASM: encoding: [0x93,0x00,0x21,0x00]
 addi ra, sp, 2
 # CHECK-ASM: addi ra, sp, %lo(foo)
 # CHECK-ASM: encoding: [0x93,0x00,0bAAAA0001,A]
 # CHECK-OBJ: addi ra, sp, 0
 # CHECK-OBJ: R_RISCV_LO12
 addi ra, sp, %lo(foo)
 # CHECK-ASM-AND-OBJ: addi ra, sp, 30
 # CHECK-ASM: encoding: [0x93,0x00,0xe1,0x01]
 addi ra, sp, CONST
+# CHECK-ASM-AND-OBJ: addi ra, sp, 0
+# CHECK-ASM: encoding: [0x93,0x00,0x01,0x00]
+addi ra, sp, (0)
+# CHECK-ASM-AND-OBJ: addi ra, sp, 156
+# CHECK-ASM: encoding: [0x93,0x00,0xc1,0x09]
+addi ra, sp, (0xff-99)
 # CHECK-ASM-AND-OBJ: slti a0, a2, -20
 # CHECK-ASM: encoding: [0x13,0x25,0xc6,0xfe]
 slti a0, a2, -20
 # CHECK-ASM-AND-OBJ: sltiu s2, s3, 80
 # CHECK-ASM: encoding: [0x13,0xb9,0x09,0x05]
 sltiu s2, s3, 0x50
 # CHECK-ASM-AND-OBJ: xori tp, t1, -99
 # CHECK-ASM: encoding: [0x13,0x42,0xd3,0xf9]