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Differential D57284

AMDGPU/GlobalISel: Legalize select for pointer types
ClosedPublic

Authored by arsenm on Jan 26 2019, 9:40 AM.

Details

Reviewers
tstellar
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Jan 26 2019, 9:40 AM
Herald added subscribers: volkan, t-tye, tpr and 8 others. · View Herald TranscriptJan 26 2019, 9:40 AM
arsenm updated this revision to Diff 184523.Jan 31 2019, 9:14 AM

Rebase, handle vectors

Herald added a subscriber: Petar.Avramovic. · View Herald TranscriptJan 31 2019, 9:14 AM
tstellar accepted this revision.Feb 1 2019, 4:08 PM

LGTM.

This revision is now accepted and ready to land.Feb 1 2019, 4:08 PM
arsenm closed this revision.Feb 2 2019, 3:31 PM

r352974

Revision Contents

PathSize
lib/
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
168 lines

Diff 183707

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines auto &Atomics = getActionDefinitionsBuilder(
.legalFor({{S32, GlobalPtr}, {S32, LocalPtr}, .legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
{S64, GlobalPtr}, {S64, LocalPtr}}); {S64, GlobalPtr}, {S64, LocalPtr}});
if (ST.hasFlatAddressSpace()) { if (ST.hasFlatAddressSpace()) {
Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}}); Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
} }
// TODO: Pointer types, any 32-bit or 64-bit vector // TODO: Pointer types, any 32-bit or 64-bit vector
getActionDefinitionsBuilder(G_SELECT) getActionDefinitionsBuilder(G_SELECT)
.legalFor({{S32, S1}, {S64, S1}, {V2S32, S1}, {V2S16, S1}}) .legalForCartesianProduct({S32, S64, V2S32, V2S16, GlobalPtr, LocalPtr,
FlatPtr, PrivatePtr}, {S1})
.clampScalar(0, S32, S64) .clampScalar(0, S32, S64)
.scalarize(0); .scalarize(0)
.legalIf(all(isPointer(0), typeIs(1, S1)));
// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can // TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
// be more flexible with the shift amount type. // be more flexible with the shift amount type.
auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR}) auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
.legalFor({{S32, S32}, {S64, S32}}); .legalFor({{S32, S32}, {S64, S32}});
if (ST.has16BitInsts()) if (ST.has16BitInsts())
Shifts.legalFor({{S16, S32}, {S16, S16}}); Shifts.legalFor({{S16, S32}, {S16, S16}});
else else
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines bb.0:
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = G_CONSTANT i32 0 %3:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %2, %3 %4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(<2 x s16>) = G_SELECT %4, %0, %1 %5:_(<2 x s16>) = G_SELECT %4, %0, %1
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
---
name: test_select_p0
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p0) = COPY $vgpr1_vgpr2
%3:_(p0) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
---
name: test_select_p1
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p1) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p1) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p1)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p1) = COPY $vgpr1_vgpr2
%3:_(p1) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p1) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
---
name: test_select_p2
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_p2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p2) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p2) = COPY $vgpr2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p2) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p2)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p2) = COPY $vgpr1
%3:_(p2) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p2) = G_SELECT %4, %2, %3
$vgpr0 = COPY %5
...
---
name: test_select_p3
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_p3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p3) = COPY $vgpr2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p3)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p3) = COPY $vgpr1
%3:_(p3) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p3) = G_SELECT %4, %2, %3
$vgpr0 = COPY %5
...
---
name: test_select_p4
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p4) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p4) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p4) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p4)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p4) = COPY $vgpr1_vgpr2
%3:_(p4) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p4) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...
---
name: test_select_p5
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: test_select_p5
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(p5) = COPY $vgpr2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0 = COPY [[SELECT]](p5)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p5) = COPY $vgpr1
%3:_(p5) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p5) = G_SELECT %4, %2, %3
$vgpr0 = COPY %5
...
---
name: test_select_p999
body: |
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
; CHECK-LABEL: name: test_select_p999
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr1_vgpr2
; CHECK: [[COPY2:%[0-9]+]]:_(p999) = COPY $vgpr3_vgpr4
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[SELECT:%[0-9]+]]:_(p999) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](p999)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
%2:_(p999) = COPY $vgpr1_vgpr2
%3:_(p999) = COPY $vgpr3_vgpr4
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p999) = G_SELECT %4, %2, %3
$vgpr0_vgpr1 = COPY %5
...