[X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions.

[andreadb]

Summary

This is a follow-up of D57056.

On Jaguar, we need to account for an additional operand latency of 6cy (caused by bypass delays) in the case of scalar_int-to-float conversions.
The latency of (V)CVTSI2S(S|D) should be f+3; In this context, f is a bypass delay of 6cy (see AMD fam16h SOG).

This patch marks the input gpr operand as ReadIntToFpu, so that we correctly account for that delay. That quantity has then be subtacted to the opcode latency (which should just be 3cy).

I verified that latency/throughput numbers from llvm-mca have improved, and now they better match what is reported by perf on Jaguar. That being said, I still see cases where the IPC as reported by llvm-mca doesn't quite match the IPC from perf.
Example:

vcvtsi2ss %ecx, %xmm0, %xmm0    # Should tend to IPC: 0.33. Perf reports IPC: 0.25 (one cvt every 4cy).

I suspect that local forwarding might be disabled for it; it looks like users have to wait for an extra +1cy. That would explain the 0.25. For now I decided to go with what is in the documents, so we always assume a +3cy latency.

Latency for the RM variants has changed (it has slightly improved). However, we need another patch to fix the number of opcodes (it should be 1, not 2).

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

433

Update this FIXME comment and mention local forwarding?

[andreadb]

Patch updated.

I verified that the int-to-fp convert latency is 4cy (instead of 3cy) if we exclude the extra 6cy of bypass delay.
So, I went ahead and set the latency directly to 4cy.

I've also verified by running some microbenchmarks that the RM variants have a latency of ~9cy (5cy for the load opcode + 4cy of convert). That latency seems consistent with what I found when testing the RR variants. The only difference for the RM variants is the number of opcodes (it is 1 COP instead of 2 COPs).
So, I went ahead and fixed all those writes in this patch (rather than splitting the change in two patches).

[RKSimon]

LGTM

[RKSimon]

lib/Target/X86/X86InstrSSE.td

880

One minor comment - we should probably add this to the avx512f equivalents for consistency.

[andreadb]

Patch updated.
Addressed review comment.

[RKSimon]

LGTM with one more minor

lib/Target/X86/X86InstrAVX512.td

7550 ↗

(On Diff #184091)

[sched, ReadDefault, ReadInt2Fpu]

lib/Target/X86/X86InstrSSE.td

 }
 
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Conversion Instructions
 //===----------------------------------------------------------------------===//
 
 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
                      SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
-                     string asm, X86FoldableSchedWrite sched> {
+                     string asm, X86FoldableSchedWrite sched,
+                     SchedRead Int2Fpu = ReadDefault> {
   def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
                         [(set DstRC:$dst, (OpNode SrcRC:$src))]>,
-                        Sched<[sched]>;
+                        Sched<[sched, Int2Fpu]>;
   def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
                         [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>,
                         Sched<[sched.Folded]>;
 }
 
 multiclass sse12_cvt_p<bits<8> opc, RegisterClass RC, X86MemOperand x86memop,
                        ValueType DstTy, ValueType SrcTy, PatFrag ld_frag,
                        string asm, Domain d, X86FoldableSchedWrite sched> {

 }
 
 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
                           X86MemOperand x86memop, string asm,
                           X86FoldableSchedWrite sched> {
 let hasSideEffects = 0, Predicates = [UseAVX] in {
   def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
               !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
-              Sched<[sched]>;
+              Sched<[sched, ReadDefault, ReadInt2Fpu]>;
   let mayLoad = 1 in
   def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
               (ins DstRC:$src1, x86memop:$src),
               !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
            Sched<[sched.Folded, sched.ReadAfterFold]>;
 } // hasSideEffects = 0
 }
 

 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
                       "cvttsd2si\t{$src, $dst|$dst, $src}",
                       WriteCvtSD2I>, XD;
 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
                       "cvttsd2si\t{$src, $dst|$dst, $src}",
                       WriteCvtSD2I>, XD, REX_W;
 defm CVTSI2SS  : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
                       "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
-                      WriteCvtI2SS>, XS;
+                      WriteCvtI2SS, ReadInt2Fpu>, XS;
 defm CVTSI642SS : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
                       "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
-                      WriteCvtI2SS>, XS, REX_W;
+                      WriteCvtI2SS, ReadInt2Fpu>, XS, REX_W;
 defm CVTSI2SD  : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
                       "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
-                      WriteCvtI2SD>, XD;
+                      WriteCvtI2SD, ReadInt2Fpu>, XD;
 defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
                       "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
-                      WriteCvtI2SD>, XD, REX_W;
+                      WriteCvtI2SD, ReadInt2Fpu>, XD, REX_W;
 
 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0, "att">;
 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
                 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0, "att">;
 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
                     RegisterClass DstRC, X86MemOperand x86memop,
                     string asm, X86FoldableSchedWrite sched,
                     bit Is2Addr = 1> {
 let hasSideEffects = 0 in {
   def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
                   !if(Is2Addr,
                       !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
                       !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
-                  []>, Sched<[sched]>;
+                  []>, Sched<[sched, ReadDefault, ReadInt2Fpu]>;
   let mayLoad = 1 in
   def rm_Int : SI<opc, MRMSrcMem, (outs DstRC:$dst),
                   (ins DstRC:$src1, x86memop:$src2),
                   !if(Is2Addr,
                       !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
                       !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
                   []>, Sched<[sched.Folded, sched.ReadAfterFold]>;
 }

lib/Target/X86/X86ScheduleBtVer2.td

 defm : JWriteResFpuPair<WriteCvtPS2I,      [JFPU1, JSTC], 3, [1,1], 1>;
 defm : JWriteResYMMPair<WriteCvtPS2IY,     [JFPU1, JSTC], 3, [2,2], 2>;
 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 defm : JWriteResFpuPair<WriteCvtSD2I,      [JFPU1, JSTC, JFPU0, JFPA, JALU0], 7, [1,1,1,1,1], 2>;
 defm : JWriteResFpuPair<WriteCvtPD2I,      [JFPU1, JSTC], 3, [1,1], 1>;
 defm : JWriteResYMMPair<WriteCvtPD2IY,     [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 
 // FIXME: f+3 ST, LD+STC latency
-defm : JWriteResFpuPair<WriteCvtI2SS,      [JFPU1, JSTC], 9, [1,1], 2>;
+defm : JWriteResFpuPair<WriteCvtI2SS,      [JFPU1, JSTC], 3, [1,1], 2>;
 defm : JWriteResFpuPair<WriteCvtI2PS,      [JFPU1, JSTC], 3, [1,1], 1>;
 defm : JWriteResYMMPair<WriteCvtI2PSY,     [JFPU1, JSTC], 3, [2,2], 2>;
 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
-defm : JWriteResFpuPair<WriteCvtI2SD,      [JFPU1, JSTC], 9, [1,1], 2>;
+defm : JWriteResFpuPair<WriteCvtI2SD,      [JFPU1, JSTC], 3, [1,1], 2>;
 defm : JWriteResFpuPair<WriteCvtI2PD,      [JFPU1, JSTC], 3, [1,1], 1>;
 defm : JWriteResYMMPair<WriteCvtI2PDY,     [JFPU1, JSTC], 3, [2,2], 2>;
 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 
 defm : JWriteResFpuPair<WriteCvtSS2SD,      [JFPU1, JSTC], 7, [1,2], 2>;
 defm : JWriteResFpuPair<WriteCvtPS2PD,      [JFPU1, JSTC], 2, [1,1], 1>;
 defm : JWriteResYMMPair<WriteCvtPS2PDY,     [JFPU1, JSTC], 2, [2,2], 2>;
 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;

test/CodeGen/X86/sse-schedule.ll

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [4:1.00]
 ; BDVER2-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2ss:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    cvtsi2ssl (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT:    cvtsi2ssl (%rsi), %xmm0 # sched: [8:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2ssl %edi, %xmm1 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2ss:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [9:1.00]
-; BTVER2-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
+; BTVER2-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
 ; BTVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_cvtsi2ss:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    cvtsi2ssl (%rsi), %xmm0 # sched: [12:1.00]
 ; ZNVER1-SSE-NEXT:    cvtsi2ssl %edi, %xmm1 # sched: [5:1.00]
 ; ZNVER1-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [3:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
 ; BDVER2-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2ssq:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    cvtsi2ssq (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT:    cvtsi2ssq (%rsi), %xmm0 # sched: [8:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2ssq %rdi, %xmm1 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2ssq:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
-; BTVER2-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
+; BTVER2-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
 ; BTVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_cvtsi2ssq:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    cvtsi2ssq (%rsi), %xmm0 # sched: [12:1.00]
 ; ZNVER1-SSE-NEXT:    cvtsi2ssq %rdi, %xmm1 # sched: [5:1.00]
 ; ZNVER1-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [3:1.00]

test/CodeGen/X86/sse2-schedule.ll

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]
 ; BDVER2-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2sd:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    cvtsi2sdl (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT:    cvtsi2sdl (%rsi), %xmm0 # sched: [8:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2sdl %edi, %xmm1 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2sd:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [9:1.00]
-; BTVER2-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
+; BTVER2-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
 ; BTVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_cvtsi2sd:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    cvtsi2sdl (%rsi), %xmm0 # sched: [12:1.00]
 ; ZNVER1-SSE-NEXT:    cvtsi2sdl %edi, %xmm1 # sched: [5:1.00]
 ; ZNVER1-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [3:1.00]

 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
 ; BDVER2-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2sdq:
 ; BTVER2-SSE:       # %bb.0:
-; BTVER2-SSE-NEXT:    cvtsi2sdq (%rsi), %xmm0 # sched: [14:1.00]
+; BTVER2-SSE-NEXT:    cvtsi2sdq (%rsi), %xmm0 # sched: [8:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2sdq %rdi, %xmm1 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]
 ;
 ; BTVER2-LABEL: test_cvtsi2sdq:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [9:1.00]
-; BTVER2-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [14:1.00]
+; BTVER2-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [8:1.00]
 ; BTVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-SSE-LABEL: test_cvtsi2sdq:
 ; ZNVER1-SSE:       # %bb.0:
 ; ZNVER1-SSE-NEXT:    cvtsi2sdq (%rsi), %xmm0 # sched: [12:1.00]
 ; ZNVER1-SSE-NEXT:    cvtsi2sdq %rdi, %xmm1 # sched: [5:1.00]
 ; ZNVER1-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [3:1.00]

test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=500 < %s | FileCheck %s
 
-# Throughput for all the code snippet below should tend to 1.00 IPC.
+# Throughput for the AVX code snippets below should tend to 0.25 IPC.
+# Throughput for the SSE code snippets below should tend to 1.00 IPC.
 
 # LLVM-MCA-BEGIN
 vcvtsi2ss %ecx, %xmm0, %xmm0
 # LLVM-MCA-END
 
 # LLVM-MCA-BEGIN
 vcvtsi2sd %ecx, %xmm0, %xmm0
 # LLVM-MCA-END

 # LLVM-MCA-BEGIN
 movq %rcx, %xmm0
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      4503
+# CHECK-NEXT: Total Cycles:      1503
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.22
-# CHECK-NEXT: IPC:               0.11
+# CHECK-NEXT: uOps Per Cycle:    0.67
+# CHECK-NEXT: IPC:               0.33
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -     1.00    -      -      -     vcvtsi2ssl  %ecx, %xmm0, %xmm0
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      4503
+# CHECK-NEXT: Total Cycles:      1503
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.22
-# CHECK-NEXT: IPC:               0.11
+# CHECK-NEXT: uOps Per Cycle:    0.67
+# CHECK-NEXT: IPC:               0.33
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -     1.00    -      -      -     vcvtsi2sdl  %ecx, %xmm0, %xmm0
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      511
+# CHECK-NEXT: Total Cycles:      505
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.96
-# CHECK-NEXT: IPC:               0.98
+# CHECK-NEXT: uOps Per Cycle:    1.98
+# CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -     1.00    -      -      -     cvtsi2ssl %ecx, %xmm0
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      511
+# CHECK-NEXT: Total Cycles:      505
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.96
-# CHECK-NEXT: IPC:               0.98
+# CHECK-NEXT: uOps Per Cycle:    1.98
+# CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

test/tools/llvm-mca/X86/BtVer2/resources-avx1.s

 # CHECK-NEXT:  2      7     1.00                        vcvtsd2si %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        vcvtsd2si %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   vcvtsd2si (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   vcvtsd2si (%rax), %rcx
 # CHECK-NEXT:  2      7     2.00                        vcvtsd2ss %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  2      12    2.00    *                   vcvtsd2ss (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      9     1.00                        vcvtsi2sdl  %ecx, %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00                        vcvtsi2sdq  %rcx, %xmm0, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   vcvtsi2sdl  (%rax), %xmm0, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   vcvtsi2sdq  (%rax), %xmm0, %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   vcvtsi2sdl  (%rax), %xmm0, %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   vcvtsi2sdq  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00                        vcvtsi2ssl  %ecx, %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00                        vcvtsi2ssq  %rcx, %xmm0, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   vcvtsi2ssl  (%rax), %xmm0, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   vcvtsi2ssq  (%rax), %xmm0, %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   vcvtsi2ssl  (%rax), %xmm0, %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   vcvtsi2ssq  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      7     2.00                        vcvtss2sd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  2      12    2.00    *                   vcvtss2sd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      7     1.00                        vcvtss2si %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        vcvtss2si %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   vcvtss2si (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   vcvtss2si (%rax), %rcx
 # CHECK-NEXT:  1      3     1.00                        vcvttpd2dq  %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   vcvttpd2dqx (%rax), %xmm2

test/tools/llvm-mca/X86/BtVer2/resources-sse1.s

 # CHECK-NEXT:  1      3     1.00                        comiss  %xmm0, %xmm1
 # CHECK-NEXT:  1      8     1.00    *                   comiss  (%rax), %xmm1
 # CHECK-NEXT:  1      3     1.00                        cvtpi2ps  %mm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   cvtpi2ps  (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        cvtps2pi  %xmm0, %mm2
 # CHECK-NEXT:  1      8     1.00    *                   cvtps2pi  (%rax), %mm2
 # CHECK-NEXT:  2      9     1.00                        cvtsi2ssl %ecx, %xmm2
 # CHECK-NEXT:  2      9     1.00                        cvtsi2ssq %rcx, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   cvtsi2ssl (%rax), %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   cvtsi2ssl (%rax), %xmm2
 # CHECK-NEXT:  2      7     1.00                        cvtss2si  %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        cvtss2si  %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   cvtss2si  (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   cvtss2si  (%rax), %rcx
 # CHECK-NEXT:  1      3     1.00                        cvttps2pi %xmm0, %mm2
 # CHECK-NEXT:  1      8     1.00    *                   cvttps2pi (%rax), %mm2
 # CHECK-NEXT:  2      7     1.00                        cvttss2si %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        cvttss2si %xmm0, %rcx

test/tools/llvm-mca/X86/BtVer2/resources-sse2.s

 # CHECK-NEXT:  2      7     1.00                        cvtsd2si  %xmm0, %ecx
 # CHECK-NEXT:  2      7     1.00                        cvtsd2si  %xmm0, %rcx
 # CHECK-NEXT:  2      12    1.00    *                   cvtsd2si  (%rax), %ecx
 # CHECK-NEXT:  2      12    1.00    *                   cvtsd2si  (%rax), %rcx
 # CHECK-NEXT:  2      7     2.00                        cvtsd2ss  %xmm0, %xmm2
 # CHECK-NEXT:  2      12    2.00    *                   cvtsd2ss  (%rax), %xmm2
 # CHECK-NEXT:  2      9     1.00                        cvtsi2sdl %ecx, %xmm2
 # CHECK-NEXT:  2      9     1.00                        cvtsi2sdq %rcx, %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   cvtsi2sdl (%rax), %xmm2
-# CHECK-NEXT:  2      14    1.00    *                   cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT:  2      8     1.00    *                   cvtsi2sdl (%rax), %xmm2
 # CHECK-NEXT:  2      7     2.00                        cvtss2sd  %xmm0, %xmm2
 # CHECK-NEXT:  2      12    2.00    *                   cvtss2sd  (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        cvttpd2dq %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   cvttpd2dq (%rax), %xmm2
 # CHECK-NEXT:  1      3     1.00                        cvttpd2pi %xmm0, %mm2
 # CHECK-NEXT:  1      8     1.00    *                   cvttpd2pi (%rax), %mm2
 # CHECK-NEXT:  1      3     1.00                        cvttps2dq %xmm0, %xmm2
 # CHECK-NEXT:  1      8     1.00    *                   cvttps2dq (%rax), %xmm2