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Differential D57074

AMDGPU/GlobalISel: Fix shift legalization for non-power-of-2
ClosedPublic

Authored by arsenm on Jan 22 2019, 5:18 PM.

Details

Reviewers
tstellar
rampitec
Summary

clampScalar doesn't do anything for non-power-of-2 in range.
There should probably be a combination rule to reduce the number
of matching rules.

Diff Detail

Event Timeline

arsenm created this revision.Jan 22 2019, 5:18 PM
Herald added subscribers: volkan, t-tye, tpr and 8 others. · View Herald TranscriptJan 22 2019, 5:18 PM
arsenm added a comment.Feb 8 2019, 6:46 AM

ping

Herald added a subscriber: Petar.Avramovic. · View Herald TranscriptFeb 8 2019, 6:46 AM
tstellar accepted this revision.Feb 8 2019, 6:48 AM

LGTM.

This revision is now accepted and ready to land.Feb 8 2019, 6:48 AM
arsenm closed this revision.Feb 8 2019, 7:06 AM

r353526

Revision Contents

PathSize
lib/
Target/
AMDGPU/
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
110 lines

Diff 183003

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 329 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can // TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
// be more flexible with the shift amount type. // be more flexible with the shift amount type.
auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR}) auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
.legalFor({{S32, S32}, {S64, S32}}); .legalFor({{S32, S32}, {S64, S32}});
if (ST.has16BitInsts()) { if (ST.has16BitInsts()) {
Shifts.legalFor({{S16, S32}, {S16, S16}}); Shifts.legalFor({{S16, S32}, {S16, S16}});
Shifts.clampScalar(0, S16, S64); Shifts.clampScalar(0, S16, S64);
} else Shifts.widenScalarToNextPow2(0, 16);
} else {
Shifts.clampScalar(0, S32, S64); Shifts.clampScalar(0, S32, S64);
Shifts.widenScalarToNextPow2(0, 32);
}
Shifts.clampScalar(1, S32, S32); Shifts.clampScalar(1, S32, S32);
// FIXME: When RegBankSelect inserts copies, it will only create new // FIXME: When RegBankSelect inserts copies, it will only create new
// registers with scalar types. This means we can end up with // registers with scalar types. This means we can end up with
// G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
// operands. In assert builds, the instruction selector will assert // operands. In assert builds, the instruction selector will assert
// if it sees a generic instruction which isn't legal, so we need to // if it sees a generic instruction which isn't legal, so we need to
// tell it that scalar types are legal for pointer operands // tell it that scalar types are legal for pointer operands
setAction({G_GEP, S64}, Legal); setAction({G_GEP, S64}, Legal);
▲ Show 20 Lines • Show All 133 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
... ...
--- ---
name: test_shl_i8_i8 name: test_shl_i8_i8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_shl_i8_i8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_shl_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SHL %2, %3 %4:_(s8) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
... ...
---
name: test_shl_i7_i7
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_shl_i7_i7
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_shl_i7_i7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_i7_i7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1
%4:_(s7) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
---
name: test_shl_i24_i32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_shl_i24_i32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY3]](s32)
; VI-LABEL: name: test_shl_i24_i32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; VI: $vgpr0 = COPY [[COPY3]](s32)
; GFX9-LABEL: name: test_shl_i24_i32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; GFX9: $vgpr0 = COPY [[COPY3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
%3:_(s24) = G_SHL %2, %1
%4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4
...