GlobalISel: Combine trunc with constant

[arsenm]

Summary

Fixes up the legalization created by requiring
a 32-bit shift amount type when producing a 64-bit
shift on AMDGPU.

[aemerson]

Just checking, this is dependent on D55639?

[aditya_nandakumar]

Is this required for correctness? This looks like something that would fall in an actual combiner (vs the artifact combiner).

[arsenm]

It depends on it only really for the tests. It shouldn’t be needed for correctness

[aditya_nandakumar]

In D56706#1358590, @arsenm wrote:

It depends on it only really for the tests. It shouldn’t be needed for correctness

The legalizer artifact combiner was originally intended only to combine away legalization artifacts - which include extends, truncates, merges, build_vectors and not for generic combines. This change looks like it should belong in CombinerHelper.

[arsenm]

This was reimplemented and committed by D69367

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
           {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), MIBShAmt});
       Builder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {MIBShl, MIBShAmt});
       markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
       return true;
     }
     return tryFoldImplicitDef(MI, DeadInsts);
   }
 
+  bool tryCombineTrunc(MachineInstr &MI,
+                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
+    if (MI.getOpcode() != TargetOpcode::G_TRUNC)
+      return false;
+
+    Builder.setInstr(MI);
+
+    // t1 = trunc (g_constant t0) -> g_constant t1
+    int64_t Cst;
+    unsigned SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
+
+    if (mi_match(SrcReg, MRI, m_ICst(Cst))) {
+      unsigned DstReg = MI.getOperand(0).getReg();
+      if (isInstUnsupported({TargetOpcode::G_CONSTANT, {MRI.getType(DstReg)}}))
+        return false;
+
+      Builder.buildConstant(DstReg, Cst);
+      markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
+      return true;
+    }
+
+    return false;
+  }
+
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts) {
     unsigned Opcode = MI.getOpcode();
     if (Opcode != TargetOpcode::G_ANYEXT && Opcode != TargetOpcode::G_ZEXT &&
         Opcode != TargetOpcode::G_SEXT)
       return false;
 
bool tryCombineInstruction(MachineInstr &MI,
     case TargetOpcode::G_SEXT:
       return tryCombineSExt(MI, DeadInsts);
     case TargetOpcode::G_UNMERGE_VALUES:
       return tryCombineMerges(MI, DeadInsts);
     case TargetOpcode::G_TRUNC: {
       bool Changed = false;
       for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
         Changed |= tryCombineInstruction(Use, DeadInsts);
-      return Changed;
+
+      if (Changed)
+        return true;
+      return tryCombineTrunc(MI, DeadInsts);
     }
     }
   }
 
 private:
   /// Mark MI as dead. If a def of one of MI's operands, DefMI, would also be
   /// dead due to MI being killed, then mark DefMI as dead too.
   /// Some of the combines (extends(trunc)), try to walk through redundant

test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_sext_trunc_i64_i32_i64
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[TRUNC]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_TRUNC %0
     %2:_(s64) = G_SEXT %1
     $vgpr0_vgpr1 = COPY %2
 ...
 
 ---

test/CodeGen/X86/GlobalISel/add-ext.ll

 ; Throw in a scale (left shift) because an LEA can do that too.
 ; Use a negative constant (LEA displacement) to verify that's handled correctly.
 
 define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) {
 ; CHECK-LABEL: add_nsw_sext_lsh_add:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addl $-5, %edi
 ; CHECK-NEXT:    movslq %edi, %rax
-; CHECK-NEXT:    movq $3, %rcx
-; CHECK:         retq
+; CHECK-NEXT:    shlq $3, %rax
+; CHECK-NEXT:    addq %rsi, %rax
+; CHECK-NEXT:    retq
 
   %add = add nsw i32 %i, -5
   %ext = sext i32 %add to i64
   %shl = shl i64 %ext, 3
   %idx = add i64 %x, %shl
   ret i64 %idx
 }
 

 
 ; A bigger win can be achieved when there is more than one use of the
 ; sign extended value. In this case, we can eliminate sign extension
 ; instructions plus use more efficient addressing modes for memory ops.
 
 define void @PR20134(i32* %a, i32 %i) {
 ; CHECK-LABEL: PR20134:
 ; CHECK:       # %bb.0:
-; CHECK:         movq    $4, %rax
-; CHECK-NEXT:    leal    1(%rsi), %ecx
-; CHECK-NEXT:    movslq  %ecx, %rcx
-; CHECK-NEXT:    imulq   %rax, %rcx
-; CHECK-NEXT:    leaq    (%rdi,%rcx), %rcx
-; CHECK-NEXT:    leal    2(%rsi), %edx
-; CHECK-NEXT:    movslq  %edx, %rdx
-; CHECK-NEXT:    imulq   %rax, %rdx
-; CHECK-NEXT:    leaq    (%rdi,%rdx), %rdx
-; CHECK-NEXT:    movl    (%rdx), %edx
-; CHECK-NEXT:    addl    (%rcx), %edx
-; CHECK-NEXT:    movslq  %esi, %rcx
-; CHECK-NEXT:    imulq   %rax, %rcx
-; CHECK-NEXT:    leaq    (%rdi,%rcx), %rax
-; CHECK-NEXT:    movl    %edx, (%rax)
+; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:    movq $4, %rax
+; CHECK-NEXT:    leal 1(%rsi), %ecx
+; CHECK-NEXT:    movslq %ecx, %rcx
+; CHECK-NEXT:    imulq %rax, %rcx
+; CHECK-NEXT:    leaq (%rdi,%rcx), %rcx
+; CHECK-NEXT:    leal 2(%rsi), %edx
+; CHECK-NEXT:    movslq %edx, %rdx
+; CHECK-NEXT:    imulq %rax, %rdx
+; CHECK-NEXT:    leaq (%rdi,%rdx), %rdx
+; CHECK-NEXT:    movl (%rdx), %edx
+; CHECK-NEXT:    addl (%rcx), %edx
+; CHECK-NEXT:    movslq %esi, %rcx
+; CHECK-NEXT:    imulq %rax, %rcx
+; CHECK-NEXT:    leaq (%rdi,%rcx), %rax
+; CHECK-NEXT:    movl %edx, (%rax)
 ; CHECK-NEXT:    retq
 
   %add1 = add nsw i32 %i, 1
   %idx1 = sext i32 %add1 to i64
   %gep1 = getelementptr i32, i32* %a, i64 %idx1
   %load1 = load i32, i32* %gep1, align 4
 
   %add2 = add nsw i32 %i, 2
   %idx2 = sext i32 %add2 to i64
   %gep2 = getelementptr i32, i32* %a, i64 %idx2
   %load2 = load i32, i32* %gep2, align 4
 
   %add3 = add i32 %load1, %load2
   %idx3 = sext i32 %i to i64
   %gep3 = getelementptr i32, i32* %a, i64 %idx3
   store i32 %add3, i32* %gep3, align 4
   ret void
 }
 
 ; The same as @PR20134 but sign extension is replaced with zero extension
 define void @PR20134_zext(i32* %a, i32 %i) {
-; CHECK: # %bb.0:
-; CHECK:         movq    $4, %rax
-; CHECK-NEXT:    leal    1(%rsi), %ecx
-; CHECK-NEXT:    imulq   %rax, %rcx
-; CHECK-NEXT:    leaq    (%rdi,%rcx), %rcx
-; CHECK-NEXT:    leal    2(%rsi), %edx
-; CHECK-NEXT:    imulq   %rax, %rdx
-; CHECK-NEXT:    leaq    (%rdi,%rdx), %rdx
-; CHECK-NEXT:    movl    (%rdx), %edx
-; CHECK-NEXT:    addl    (%rcx), %edx
-; CHECK-NEXT:    imulq   %rax, %rsi
-; CHECK-NEXT:    leaq    (%rdi,%rsi), %rax
-; CHECK-NEXT:    movl    %edx, (%rax)
+; CHECK-LABEL: PR20134_zext:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:    movq $4, %rax
+; CHECK-NEXT:    leal 1(%rsi), %ecx
+; CHECK-NEXT:    imulq %rax, %rcx
+; CHECK-NEXT:    leaq (%rdi,%rcx), %rcx
+; CHECK-NEXT:    leal 2(%rsi), %edx
+; CHECK-NEXT:    imulq %rax, %rdx
+; CHECK-NEXT:    leaq (%rdi,%rdx), %rdx
+; CHECK-NEXT:    movl (%rdx), %edx
+; CHECK-NEXT:    addl (%rcx), %edx
+; CHECK-NEXT:    imulq %rax, %rsi
+; CHECK-NEXT:    leaq (%rdi,%rsi), %rax
+; CHECK-NEXT:    movl %edx, (%rax)
 ; CHECK-NEXT:    retq
 
   %add1 = add nuw i32 %i, 1
   %idx1 = zext i32 %add1 to i64
   %gep1 = getelementptr i32, i32* %a, i64 %idx1
   %load1 = load i32, i32* %gep1, align 4
 
   %add2 = add nuw i32 %i, 2

test/CodeGen/X86/GlobalISel/ashr-scalar.ll

; X64-NEXT:    retq
   %res = ashr i64 %arg1, %arg2
   ret i64 %res
 }
 
 define i64 @test_ashr_i64_imm(i64 %arg1) {
 ; X64-LABEL: test_ashr_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    sarq $5, %rax
 ; X64-NEXT:    retq
   %res = ashr i64 %arg1, 5
   ret i64 %res
 }
 
 define i64 @test_ashr_i64_imm1(i64 %arg1) {
 ; X64-LABEL: test_ashr_i64_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $1, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    sarq %rax
 ; X64-NEXT:    retq
   %res = ashr i64 %arg1, 1
   ret i64 %res
 }
 
 define i32 @test_ashr_i32(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_ashr_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    sarl %cl, %eax
 ; X64-NEXT:    retq
   %res = ashr i32 %arg1, %arg2
   ret i32 %res
 }
 
 define i32 @test_ashr_i32_imm(i32 %arg1) {
 ; X64-LABEL: test_ashr_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    sarl $5, %eax
 ; X64-NEXT:    retq
   %res = ashr i32 %arg1, 5
   ret i32 %res
 }
 
 define i32 @test_ashr_i32_imm1(i32 %arg1) {
 ; X64-LABEL: test_ashr_i32_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $1, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    sarl %eax
 ; X64-NEXT:    retq
   %res = ashr i32 %arg1, 1
   ret i32 %res
 }
 
 define i16 @test_ashr_i16(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_ashr_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    sarw %cl, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %a2 = trunc i32 %arg2 to i16
   %res = ashr i16 %a, %a2
   ret i16 %res
 }
 
 define i16 @test_ashr_i16_imm(i32 %arg1) {
 ; X64-LABEL: test_ashr_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    sarw %cl, %ax
+; X64-NEXT:    sarw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = ashr i16 %a, 5
   ret i16 %res
 }
 
 define i16 @test_ashr_i16_imm1(i32 %arg1) {
 ; X64-LABEL: test_ashr_i16_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $1, %cx
-; X64-NEXT:    sarw %cl, %ax
+; X64-NEXT:    sarw %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = ashr i16 %a, 1
   ret i16 %res
 }
 
 define i8 @test_ashr_i8(i32 %arg1, i32 %arg2) {

test/CodeGen/X86/GlobalISel/ext-x86-64.ll

; X64-NEXT:    retq
   %r = zext i1 %val to i64
   ret i64 %r
 }
 
 define i64 @test_sext_i8(i8 %val) {
 ; X64-LABEL: test_sext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movq $56, %rcx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    movq $56, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    shlq $56, %rax
+; X64-NEXT:    sarq $56, %rax
 ; X64-NEXT:    retq
   %r = sext i8 %val to i64
   ret i64 %r
 }
 
 define i64 @test_sext_i16(i16 %val) {
 ; X64-LABEL: test_sext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movq $48, %rcx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    movq $48, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    shlq $48, %rax
+; X64-NEXT:    sarq $48, %rax
 ; X64-NEXT:    retq
   %r = sext i16 %val to i64
   ret i64 %r
 }
 
 ; TODO enable after selection supported
 ;define i64 @test_sext_i32(i32 %val) {
 ;  %r = sext i32 %val to i64
 ;  ret i64 %r
 ;}
 

test/CodeGen/X86/GlobalISel/ext.ll

; X32-NEXT:    retl
   %r = zext i16 %val to i32
   ret i32 %r
 }
 
 define i32 @test_sext_i8(i8 %val) {
 ; X64-LABEL: test_sext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $24, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    movl $24, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    shll $24, %eax
+; X64-NEXT:    sarl $24, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: test_sext_i8:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    retl
   %r = sext i8 %val to i32
   ret i32 %r
 }
 
 define i32 @test_sext_i16(i16 %val) {
 ; X64-LABEL: test_sext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $16, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    movl $16, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    shll $16, %eax
+; X64-NEXT:    sarl $16, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: test_sext_i16:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movswl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    retl
   %r = sext i16 %val to i32
   ret i32 %r
 }
 

test/CodeGen/X86/GlobalISel/gep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64_GISEL
 ; RUN: llc -mtriple=x86_64-linux-gnu              -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
 
 define i32* @test_gep_i8(i32 *%arr, i8 %ind) {
 ; X64_GISEL-LABEL: test_gep_i8:
 ; X64_GISEL:       # %bb.0:
 ; X64_GISEL-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64_GISEL-NEXT:    movq $4, %rax
-; X64_GISEL-NEXT:    movq $56, %rcx
-; X64_GISEL-NEXT:    shlq %cl, %rsi
-; X64_GISEL-NEXT:    movq $56, %rcx
-; X64_GISEL-NEXT:    sarq %cl, %rsi
+; X64_GISEL-NEXT:    shlq $56, %rsi
+; X64_GISEL-NEXT:    sarq $56, %rsi
 ; X64_GISEL-NEXT:    imulq %rax, %rsi
 ; X64_GISEL-NEXT:    leaq (%rdi,%rsi), %rax
 ; X64_GISEL-NEXT:    retq
 ;
 ; X64-LABEL: test_gep_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64-NEXT:    movsbq %sil, %rax
; X64-NEXT:    retq
   ret i32* %arrayidx
 }
 
 define i32* @test_gep_i16(i32 *%arr, i16 %ind) {
 ; X64_GISEL-LABEL: test_gep_i16:
 ; X64_GISEL:       # %bb.0:
 ; X64_GISEL-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64_GISEL-NEXT:    movq $4, %rax
-; X64_GISEL-NEXT:    movq $48, %rcx
-; X64_GISEL-NEXT:    shlq %cl, %rsi
-; X64_GISEL-NEXT:    movq $48, %rcx
-; X64_GISEL-NEXT:    sarq %cl, %rsi
+; X64_GISEL-NEXT:    shlq $48, %rsi
+; X64_GISEL-NEXT:    sarq $48, %rsi
 ; X64_GISEL-NEXT:    imulq %rax, %rsi
 ; X64_GISEL-NEXT:    leaq (%rdi,%rsi), %rax
 ; X64_GISEL-NEXT:    retq
 ;
 ; X64-LABEL: test_gep_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64-NEXT:    movswq %si, %rax

test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir

registers:
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: test_sext_i1
     ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s8)
     ; CHECK: $rax = COPY [[ASHR]](s64)
     ; CHECK: RET 0, implicit $rax
     %0(s8) = COPY $dil
     %1(s1) = G_TRUNC %0(s8)
     %2(s64) = G_SEXT %1(s1)
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 

test/CodeGen/X86/GlobalISel/lshr-scalar.ll

; X64-NEXT:    retq
   %res = lshr i64 %arg1, %arg2
   ret i64 %res
 }
 
 define i64 @test_lshr_i64_imm(i64 %arg1) {
 ; X64-LABEL: test_lshr_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    shrq %cl, %rax
+; X64-NEXT:    shrq $5, %rax
 ; X64-NEXT:    retq
   %res = lshr i64 %arg1, 5
   ret i64 %res
 }
 
 define i64 @test_lshr_i64_imm1(i64 %arg1) {
 ; X64-LABEL: test_lshr_i64_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $1, %rcx
-; X64-NEXT:    shrq %cl, %rax
+; X64-NEXT:    shrq %rax
 ; X64-NEXT:    retq
   %res = lshr i64 %arg1, 1
   ret i64 %res
 }
 
 define i32 @test_lshr_i32(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_lshr_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrl %cl, %eax
 ; X64-NEXT:    retq
   %res = lshr i32 %arg1, %arg2
   ret i32 %res
 }
 
 define i32 @test_lshr_i32_imm(i32 %arg1) {
 ; X64-LABEL: test_lshr_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    shrl %cl, %eax
+; X64-NEXT:    shrl $5, %eax
 ; X64-NEXT:    retq
   %res = lshr i32 %arg1, 5
   ret i32 %res
 }
 
 define i32 @test_lshr_i32_imm1(i32 %arg1) {
 ; X64-LABEL: test_lshr_i32_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $1, %ecx
-; X64-NEXT:    shrl %cl, %eax
+; X64-NEXT:    shrl %eax
 ; X64-NEXT:    retq
   %res = lshr i32 %arg1, 1
   ret i32 %res
 }
 
 define i16 @test_lshr_i16(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_lshr_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrw %cl, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %a2 = trunc i32 %arg2 to i16
   %res = lshr i16 %a, %a2
   ret i16 %res
 }
 
 define i16 @test_lshr_i16_imm(i32 %arg1) {
 ; X64-LABEL: test_lshr_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    shrw %cl, %ax
+; X64-NEXT:    shrw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = lshr i16 %a, 5
   ret i16 %res
 }
 
 define i16 @test_lshr_i16_imm1(i32 %arg1) {
 ; X64-LABEL: test_lshr_i16_imm1:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $1, %cx
-; X64-NEXT:    shrw %cl, %ax
+; X64-NEXT:    shrw %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = lshr i16 %a, 1
   ret i16 %res
 }
 
 define i8 @test_lshr_i8(i32 %arg1, i32 %arg2) {

test/CodeGen/X86/GlobalISel/shl-scalar.ll

; X64-NEXT:    retq
   %res = shl i64 %arg1, %arg2
   ret i64 %res
 }
 
 define i64 @test_shl_i64_imm(i64 %arg1) {
 ; X64-LABEL: test_shl_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    shlq %cl, %rax
+; X64-NEXT:    shlq $5, %rax
 ; X64-NEXT:    retq
   %res = shl i64 %arg1, 5
   ret i64 %res
 }
 
 define i64 @test_shl_i64_imm1(i64 %arg1) {
 ; X64-LABEL: test_shl_i64_imm1:
 ; X64:       # %bb.0:
-; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $1, %rcx
-; X64-NEXT:    shlq %cl, %rax
+; X64-NEXT:    leaq (%rdi,%rdi), %rax
 ; X64-NEXT:    retq
   %res = shl i64 %arg1, 1
   ret i64 %res
 }
 
 define i32 @test_shl_i32(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_shl_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shll %cl, %eax
 ; X64-NEXT:    retq
   %res = shl i32 %arg1, %arg2
   ret i32 %res
 }
 
 define i32 @test_shl_i32_imm(i32 %arg1) {
 ; X64-LABEL: test_shl_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    shll %cl, %eax
+; X64-NEXT:    shll $5, %eax
 ; X64-NEXT:    retq
   %res = shl i32 %arg1, 5
   ret i32 %res
 }
 
 define i32 @test_shl_i32_imm1(i32 %arg1) {
 ; X64-LABEL: test_shl_i32_imm1:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $1, %ecx
-; X64-NEXT:    shll %cl, %eax
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi), %eax
 ; X64-NEXT:    retq
   %res = shl i32 %arg1, 1
   ret i32 %res
 }
 
 define i16 @test_shl_i16(i32 %arg1, i32 %arg2) {
 ; X64-LABEL: test_shl_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shlw %cl, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %a2 = trunc i32 %arg2 to i16
   %res = shl i16 %a, %a2
   ret i16 %res
 }
 
 define i16 @test_shl_i16_imm(i32 %arg1) {
 ; X64-LABEL: test_shl_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    shlw %cl, %ax
+; X64-NEXT:    shlw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = shl i16 %a, 5
   ret i16 %res
 }
 
 define i16 @test_shl_i16_imm1(i32 %arg1) {
 ; X64-LABEL: test_shl_i16_imm1:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $1, %cx
-; X64-NEXT:    shlw %cl, %ax
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi), %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
   %res = shl i16 %a, 1
   ret i16 %res
 }
 
 define i8 @test_shl_i8(i32 %arg1, i32 %arg2) {

test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir

registers:
   - { id: 3, class: _ }
 body:             |
   bb.1.entry:
     liveins: $edi
 
     ; CHECK-LABEL: name: int8_to_float
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
     ; CHECK: RET 0, implicit $xmm0
     %1:_(s32) = COPY $edi
     %0:_(s8) = G_TRUNC %1(s32)
     %2:_(s32) = G_SITOFP %0(s8)
     %3:_(s128) = G_ANYEXT %2(s32)
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1.entry:
     liveins: $edi
 
     ; CHECK-LABEL: name: int16_to_float
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
     ; CHECK: RET 0, implicit $xmm0
     %1:_(s32) = COPY $edi
     %0:_(s16) = G_TRUNC %1(s32)
     %2:_(s32) = G_SITOFP %0(s16)
     %3:_(s128) = G_ANYEXT %2(s32)
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1.entry:
     liveins: $edi
 
     ; CHECK-LABEL: name: int8_to_double
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
     ; CHECK: RET 0, implicit $xmm0
     %1:_(s32) = COPY $edi
     %0:_(s8) = G_TRUNC %1(s32)
     %2:_(s64) = G_SITOFP %0(s8)
     %3:_(s128) = G_ANYEXT %2(s64)
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1.entry:
     liveins: $edi
 
     ; CHECK-LABEL: name: int16_to_double
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
     ; CHECK: RET 0, implicit $xmm0
     %1:_(s32) = COPY $edi
     %0:_(s16) = G_TRUNC %1(s32)
     %2:_(s64) = G_SITOFP %0(s16)
     %3:_(s128) = G_ANYEXT %2(s64)