[PPC64] Fix RelType in checkInt and checkAlignment diagnsotics.

[sfertile]

Summary

In the PPC64 target we map toc-relative relocations, dynamic thread pointer relative relocations and got relocations into a corresponding ADDR16 relocation type for handling in relocateOne. This patch saves the orignal RelType before mapping to an ADDR16 relocation so that any diagnostic messages will not mistakenly use the mapped type.

[ruiu]

ELF/Arch/PPC64.cpp

615–617 ↗

(On Diff #180697)

Where are you using this variable to check whether toc-optimize should be done or not?

[sfertile]

ELF/Arch/PPC64.cpp

615–617 ↗

(On Diff #180697)

I'm not using the new variable since the call to isTocOptType comes before we map the relocations to an addr16 type and Type is still the original type. With the comment I'm trying to convey there is an explicit dependency between isTocOptType and toAddr16Rel.

[ruiu]

LGTM

[grimar]

ELF/Arch/PPC64.cpp

614 ↗

(On Diff #180697)

Please remove this excessive empty line.

lld/trunk/ELF/Arch/PPC64.cpp

static bool isTocOptType(RelType Type) {
   case R_PPC64_TOC16_LO:
     return true;
   default:
     return false;
   }
 }
 
 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
-  // We need to save the original relocation type to determine if we should
-  // toc-optimize the instructions being relocated.
+  // We need to save the original relocation type to use in diagnostics, and
+  // use the original type to determine if we should toc-optimize the
+  // instructions being relocated.
+  RelType OriginalType = Type;
   bool ShouldTocOptimize =  isTocOptType(Type);
-  // For TOC-relative and GOT-indirect relocations, proceed in terms of the
-  // corresponding ADDR16 relocation type.
+  // For dynamic thread pointer relative, toc-relative, and got-indirect
+  // relocations, proceed in terms of the corresponding ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
   case R_PPC64_ADDR14: {
     checkAlignment(Loc, Val, 4, Type);
     // Preserve the AA/LK bits in the branch instruction
     uint8_t AALK = Loc[3];
     write16(Loc + 2, (AALK & 3) | (Val & 0xfffc));
     break;
   }
   case R_PPC64_ADDR16:
   case R_PPC64_TPREL16:
-    checkInt(Loc, Val, 16, Type);
+    checkInt(Loc, Val, 16, OriginalType);
     write16(Loc, Val);
     break;
   case R_PPC64_ADDR16_DS:
   case R_PPC64_TPREL16_DS: {
-    checkInt(Loc, Val, 16, Type);
+    checkInt(Loc, Val, 16, OriginalType);
     // DQ-form instructions use bits 28-31 as part of the instruction encoding
     // DS-form instructions only use bits 30-31.
     uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3;
-    checkAlignment(Loc, lo(Val), Mask + 1, Type);
+    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
     write16(Loc, (read16(Loc) & Mask) | lo(Val));
   } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
     if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
       writeInstrFromHalf16(Loc, 0x60000000);
     else
case R_PPC64_TPREL16_LO:
     write16(Loc, lo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
   case R_PPC64_TPREL16_LO_DS: {
     // DQ-form instructions use bits 28-31 as part of the instruction encoding
     // DS-form instructions only use bits 30-31.
     uint32_t Inst = readInstrFromHalf16(Loc);
     uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
-    checkAlignment(Loc, lo(Val), Mask + 1, Type);
+    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
     if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
       // When the high-adjusted part of a toc relocation evalutes to 0, it is
       // changed into a nop. The lo part then needs to be updated to use the toc
       // pointer register r2, as the base register.
       if (isInstructionUpdateForm(Inst))
         error(getErrorLocation(Loc) +
               "Can't toc-optimize an update instruction: 0x" +
               Twine::utohexstr(Inst));

lld/trunk/test/ELF/ppc64-error-missaligned-dq.s

 # REQUIRES: ppc
 #
 # RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
 # RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
 # RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
 
-# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 16 bytes
+# CHECK: improper alignment for relocation R_PPC64_TOC16_LO_DS: 0x8001 is not aligned to 16 bytes
 
         .global test
         .p2align        4
         .type   test,@function
 test:
 .Lgep:
         addis 2, 12, .TOC.-.Lgep@ha
         addi  2, 2,  .TOC.-.Lgep@l

lld/trunk/test/ELF/ppc64-error-missaligned-ds.s

 # REQUIRES: ppc
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
 # RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
 # RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
 
-# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 4 bytes
+# CHECK: improper alignment for relocation R_PPC64_TOC16_LO_DS: 0x8001 is not aligned to 4 bytes
 
         .global test
         .p2align        4
         .type   test,@function
 test:
 .Lgep:
         addis 2, 12, .TOC.-.Lgep@ha
         addi  2, 2,  .TOC.-.Lgep@l