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Differential D56320

[mips] Optimize shifts for types larger than GPR size (mips2/mips3)
ClosedPublic

Authored by abeserminji on Jan 4 2019, 8:35 AM.

Details

Reviewers
petarj
atanasyan
smaksimovic
Commits
rG4c4c0377ca6c: [mips] Optimize shifts for types larger than GPR size (mips2/mips3)
rL351059: [mips] Optimize shifts for types larger than GPR size (mips2/mips3)
Summary

With this patch, shifts are lowered to optimal number of instructions
necessary to shift types larger than the general purpose register size.

Diff Detail

Event Timeline

abeserminji created this revision.Jan 4 2019, 8:35 AM
Herald added subscribers: jrtc27, arichardson, sdardis. · View Herald TranscriptJan 4 2019, 8:35 AM
abeserminji updated this revision to Diff 180828.Jan 9 2019, 5:58 AM

Update patch for context.

atanasyan accepted this revision.Jan 9 2019, 1:29 PM

LGTM with a couple of nits

lib/Target/Mips/MipsISelLowering.cpp
2443

clang-format the if block please

4380

s/instrution/instruction/

This revision is now accepted and ready to land.Jan 9 2019, 1:29 PM
abeserminji updated this revision to Diff 181020.Jan 10 2019, 4:24 AM
abeserminji marked 2 inline comments as done.

Comments resolved.

Closed by commit rL351059: [mips] Optimize shifts for types larger than GPR size (mips2/mips3) (authored by abeserminji). · Explain WhyJan 14 2019, 4:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
10 lines
2 lines
100 lines
18 lines
test/
CodeGen/
Mips/
llvm-ir/
284 lines
286 lines
287 lines

Diff 180242

lib/Target/Mips/MipsCondMov.td

Context not available.
def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>; def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32; def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64; def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;
let usesCustomInserter = 1 in {
class D_SELECT_CLASS<RegisterOperand RC> :
PseudoSE<(outs RC:$dst1, RC:$dst2),
(ins GPR32Opnd:$cond, RC:$a1, RC:$a2, RC:$b1, RC:$b2), []>,
ISA_MIPS1_NOT_4_32;
}
def PseudoD_SELECT_I : D_SELECT_CLASS<GPR32Opnd>;
def PseudoD_SELECT_I64 : D_SELECT_CLASS<GPR64Opnd>;
Context not available.

lib/Target/Mips/MipsISelLowering.h

Context not available.
MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const; MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB, MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
bool isFPCmp, unsigned Opc) const; bool isFPCmp, unsigned Opc) const;
MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
MachineBasicBlock *BB) const;
}; };
/// Create MipsTargetLowering objects. /// Create MipsTargetLowering objects.
Context not available.

lib/Target/Mips/MipsISelLowering.cpp

Context not available.
case Mips::PseudoSELECTFP_T_D32: case Mips::PseudoSELECTFP_T_D32:
case Mips::PseudoSELECTFP_T_D64: case Mips::PseudoSELECTFP_T_D64:
return emitPseudoSELECT(MI, BB, true, Mips::BC1T); return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
case Mips::PseudoD_SELECT_I:
case Mips::PseudoD_SELECT_I64:
return emitPseudoD_SELECT(MI, BB);
} }
} }
Context not available.
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
DAG.getConstant(0, DL, VT), ShiftLeftLo); if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
SDVTList VTList = DAG.getVTList(VT, VT);
return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
: Mips::PseudoD_SELECT_I,
DL, VTList, Cond, DAG.getConstant(0, DL, VT),
ShiftLeftLo, ShiftLeftLo, Or);
}
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, DL, VT),
ShiftLeftLo);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
SDValue Ops[2] = {Lo, Hi}; SDValue Ops[2] = {Lo, Hi};
Context not available.
DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
atanasyanUnsubmitted
Done
ReplyInline Actions

clang-format the if block please

atanasyan: clang-format the `if` block please
SDVTList VTList = DAG.getVTList(VT, VT);
return DAG.getNode(
Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 : Mips::PseudoD_SELECT_I,
DL, VTList, Cond, ShiftRightHi,
IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, ShiftRightHi);
}
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
Context not available.
return BB; return BB;
} }
MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
MachineBasicBlock *BB) const {
assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of"
"conditional-move instructions.");
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
// D_SELECT substitutes two SELECT nodes that goes one after another and
// have the same condition operand. On machines which don't have
// conditional-move instrution, it reduces unnecessary branch instructions
atanasyanUnsubmitted
Done
ReplyInline Actions

s/instrution/instruction/

atanasyan: s/instrution/instruction/
// which are result of using two diamond patterns that are result of two
// SELECT pseudo instructions.
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineFunction::iterator It = ++BB->getIterator();
// thisMBB:
// ...
// TrueVal = ...
// setcc r1, r2, r3
// bNE r1, r0, copy1MBB
// fallthrough --> copy0MBB
MachineBasicBlock *thisMBB = BB;
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Transfer the remainder of BB and its successor edges to sinkMBB.
sinkMBB->splice(sinkMBB->begin(), BB,
std::next(MachineBasicBlock::iterator(MI)), BB->end());
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
// bne rs, $0, sinkMBB
BuildMI(BB, DL, TII->get(Mips::BNE))
.addReg(MI.getOperand(2).getReg())
.addReg(Mips::ZERO)
.addMBB(sinkMBB);
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
BB = copy0MBB;
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
// sinkMBB:
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
// ...
BB = sinkMBB;
// Use two PHI nodes to select two reults
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
.addReg(MI.getOperand(3).getReg())
.addMBB(thisMBB)
.addReg(MI.getOperand(5).getReg())
.addMBB(copy0MBB);
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
.addReg(MI.getOperand(4).getReg())
.addMBB(thisMBB)
.addReg(MI.getOperand(6).getReg())
.addMBB(copy0MBB);
MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
Context not available.

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Context not available.
switch(Opcode) { switch(Opcode) {
default: break; default: break;
case Mips::PseudoD_SELECT_I:
case Mips::PseudoD_SELECT_I64: {
MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
SDValue cond = Node->getOperand(0);
SDValue Hi1 = Node->getOperand(1);
SDValue Lo1 = Node->getOperand(2);
SDValue Hi2 = Node->getOperand(3);
SDValue Lo2 = Node->getOperand(4);
SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
EVT NodeTys[] = {VT, VT};
ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit()
? Mips::PseudoD_SELECT_I64
: Mips::PseudoD_SELECT_I,
DL, NodeTys, ops));
return true;
}
case ISD::ADDE: { case ISD::ADDE: {
selectAddE(Node, DL); selectAddE(Node, DL);
return true; return true;
Context not available.

test/CodeGen/Mips/llvm-ir/ashr.ll

Context not available.
define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
; MIPS-LABEL: ashr_i64: ; MIPS-LABEL: ashr_i64:
; MIPS: # %bb.0: # %entry ; MIPS: # %bb.0:
; MIPS-NEXT: srav $2, $4, $7 ; MIPS-NEXT: andi $1, $7, 32
; MIPS-NEXT: andi $6, $7, 32 ; MIPS-NEXT: bnez $1, $BB4_2
; MIPS-NEXT: beqz $6, $BB4_3 ; MIPS-NEXT: srav $3, $4, $7
; MIPS-NEXT: move $3, $2 ; MIPS-NEXT: # %bb.1:
; MIPS-NEXT: # %bb.1: # %entry ; MIPS-NEXT: srlv $1, $5, $7
; MIPS-NEXT: bnez $6, $BB4_4 ; MIPS-NEXT: not $2, $7
; MIPS-NEXT: nop ; MIPS-NEXT: sll $4, $4, 1
; MIPS-NEXT: $BB4_2: # %entry ; MIPS-NEXT: sllv $2, $4, $2
; MIPS-NEXT: jr $ra ; MIPS-NEXT: or $1, $2, $1
; MIPS-NEXT: nop ; MIPS-NEXT: move $2, $3
; MIPS-NEXT: $BB4_3: # %entry ; MIPS-NEXT: jr $ra
; MIPS-NEXT: srlv $1, $5, $7 ; MIPS-NEXT: move $3, $1
; MIPS-NEXT: not $3, $7 ; MIPS-NEXT: $BB4_2:
; MIPS-NEXT: sll $5, $4, 1 ; MIPS-NEXT: jr $ra
; MIPS-NEXT: sllv $3, $5, $3
; MIPS-NEXT: beqz $6, $BB4_2
; MIPS-NEXT: or $3, $3, $1
; MIPS-NEXT: $BB4_4:
; MIPS-NEXT: jr $ra
; MIPS-NEXT: sra $2, $4, 31 ; MIPS-NEXT: sra $2, $4, 31
; ;
; MIPS32-LABEL: ashr_i64: ; MIPS32-LABEL: ashr_i64:
Context not available.
define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MIPS-LABEL: ashr_i128: ; MIPS-LABEL: ashr_i128:
; MIPS: # %bb.0: # %entry ; MIPS: # %bb.0:
; MIPS-NEXT: addiu $sp, $sp, -8 ; MIPS-NEXT: lw $2, 28($sp)
; MIPS-NEXT: .cfi_def_cfa_offset 8 ; MIPS-NEXT: not $3, $2
; MIPS-NEXT: sw $17, 4($sp) # 4-byte Folded Spill
; MIPS-NEXT: sw $16, 0($sp) # 4-byte Folded Spill
; MIPS-NEXT: .cfi_offset 17, -4
; MIPS-NEXT: .cfi_offset 16, -8
; MIPS-NEXT: lw $25, 36($sp)
; MIPS-NEXT: addiu $1, $zero, 64 ; MIPS-NEXT: addiu $1, $zero, 64
; MIPS-NEXT: subu $11, $1, $25 ; MIPS-NEXT: subu $9, $1, $2
; MIPS-NEXT: sllv $9, $5, $11 ; MIPS-NEXT: andi $8, $2, 32
; MIPS-NEXT: andi $13, $11, 32 ; MIPS-NEXT: bnez $8, $BB5_2
; MIPS-NEXT: addiu $2, $zero, 0 ; MIPS-NEXT: srlv $11, $6, $2
; MIPS-NEXT: bnez $13, $BB5_2 ; MIPS-NEXT: # %bb.1:
; MIPS-NEXT: addiu $3, $zero, 0 ; MIPS-NEXT: srlv $1, $7, $2
; MIPS-NEXT: # %bb.1: # %entry
; MIPS-NEXT: move $3, $9
; MIPS-NEXT: $BB5_2: # %entry
; MIPS-NEXT: not $gp, $25
; MIPS-NEXT: srlv $12, $6, $25
; MIPS-NEXT: andi $8, $25, 32
; MIPS-NEXT: bnez $8, $BB5_4
; MIPS-NEXT: move $15, $12
; MIPS-NEXT: # %bb.3: # %entry
; MIPS-NEXT: srlv $1, $7, $25
; MIPS-NEXT: sll $10, $6, 1 ; MIPS-NEXT: sll $10, $6, 1
; MIPS-NEXT: sllv $10, $10, $gp ; MIPS-NEXT: sllv $10, $10, $3
; MIPS-NEXT: or $15, $10, $1 ; MIPS-NEXT: or $10, $10, $1
; MIPS-NEXT: $BB5_4: # %entry ; MIPS-NEXT: b $BB5_3
; MIPS-NEXT: addiu $10, $25, -64 ; MIPS-NEXT: move $14, $11
; MIPS-NEXT: sll $17, $4, 1 ; MIPS-NEXT: $BB5_2:
; MIPS-NEXT: srav $14, $4, $10 ; MIPS-NEXT: addiu $14, $zero, 0
; MIPS-NEXT: andi $24, $10, 32 ; MIPS-NEXT: move $10, $11
; MIPS-NEXT: bnez $24, $BB5_6 ; MIPS-NEXT: $BB5_3:
; MIPS-NEXT: move $16, $14 ; MIPS-NEXT: andi $1, $9, 32
; MIPS-NEXT: # %bb.5: # %entry ; MIPS-NEXT: bnez $1, $BB5_5
; MIPS-NEXT: srlv $1, $5, $10 ; MIPS-NEXT: sllv $11, $5, $9
; MIPS-NEXT: not $10, $10 ; MIPS-NEXT: # %bb.4:
; MIPS-NEXT: sllv $10, $17, $10 ; MIPS-NEXT: sllv $1, $4, $9
; MIPS-NEXT: or $16, $10, $1 ; MIPS-NEXT: not $9, $9
; MIPS-NEXT: $BB5_6: # %entry ; MIPS-NEXT: srl $12, $5, 1
; MIPS-NEXT: sltiu $10, $25, 64 ; MIPS-NEXT: srlv $9, $12, $9
; MIPS-NEXT: beqz $10, $BB5_8 ; MIPS-NEXT: b $BB5_6
; MIPS-NEXT: nop ; MIPS-NEXT: or $24, $1, $9
; MIPS-NEXT: $BB5_5:
; MIPS-NEXT: move $24, $11
; MIPS-NEXT: addiu $11, $zero, 0
; MIPS-NEXT: $BB5_6:
; MIPS-NEXT: addiu $15, $2, -64
; MIPS-NEXT: sll $12, $4, 1
; MIPS-NEXT: srav $13, $4, $15
; MIPS-NEXT: andi $1, $15, 32
; MIPS-NEXT: bnez $1, $BB5_9
; MIPS-NEXT: sra $9, $4, 31
; MIPS-NEXT: # %bb.7: ; MIPS-NEXT: # %bb.7:
; MIPS-NEXT: or $16, $15, $3 ; MIPS-NEXT: srlv $1, $5, $15
; MIPS-NEXT: $BB5_8: # %entry ; MIPS-NEXT: not $15, $15
; MIPS-NEXT: srav $15, $4, $25 ; MIPS-NEXT: sllv $15, $12, $15
; MIPS-NEXT: beqz $8, $BB5_20 ; MIPS-NEXT: move $25, $13
; MIPS-NEXT: move $3, $15 ; MIPS-NEXT: sltiu $13, $2, 64
; MIPS-NEXT: # %bb.9: # %entry ; MIPS-NEXT: beqz $13, $BB5_11
; MIPS-NEXT: sltiu $gp, $25, 1 ; MIPS-NEXT: or $15, $15, $1
; MIPS-NEXT: beqz $gp, $BB5_21 ; MIPS-NEXT: # %bb.8:
; MIPS-NEXT: nop ; MIPS-NEXT: b $BB5_10
; MIPS-NEXT: $BB5_10: # %entry
; MIPS-NEXT: beqz $10, $BB5_22
; MIPS-NEXT: sra $25, $4, 31
; MIPS-NEXT: $BB5_11: # %entry
; MIPS-NEXT: beqz $13, $BB5_23
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: $BB5_12: # %entry ; MIPS-NEXT: $BB5_9:
; MIPS-NEXT: beqz $8, $BB5_24 ; MIPS-NEXT: move $15, $13
; MIPS-NEXT: sltiu $13, $2, 64
; MIPS-NEXT: beqz $13, $BB5_11
; MIPS-NEXT: move $25, $9
; MIPS-NEXT: $BB5_10:
; MIPS-NEXT: or $25, $14, $24
; MIPS-NEXT: $BB5_11:
; MIPS-NEXT: sltiu $14, $2, 1
; MIPS-NEXT: beqz $14, $BB5_17
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: $BB5_13: # %entry ; MIPS-NEXT: # %bb.12:
; MIPS-NEXT: beqz $24, $BB5_25 ; MIPS-NEXT: bnez $13, $BB5_18
; MIPS-NEXT: move $4, $25
; MIPS-NEXT: $BB5_14: # %entry
; MIPS-NEXT: bnez $10, $BB5_26
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: $BB5_15: # %entry ; MIPS-NEXT: $BB5_13:
; MIPS-NEXT: beqz $gp, $BB5_27 ; MIPS-NEXT: beqz $14, $BB5_19
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: $BB5_16: # %entry ; MIPS-NEXT: $BB5_14:
; MIPS-NEXT: beqz $8, $BB5_28 ; MIPS-NEXT: bnez $8, $BB5_20
; MIPS-NEXT: move $2, $25 ; MIPS-NEXT: srav $4, $4, $2
; MIPS-NEXT: $BB5_17: # %entry ; MIPS-NEXT: $BB5_15:
; MIPS-NEXT: bnez $10, $BB5_19 ; MIPS-NEXT: srlv $1, $5, $2
; MIPS-NEXT: sllv $2, $12, $3
; MIPS-NEXT: or $3, $2, $1
; MIPS-NEXT: bnez $13, $BB5_22
; MIPS-NEXT: move $2, $4
; MIPS-NEXT: # %bb.16:
; MIPS-NEXT: b $BB5_21
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: $BB5_18: # %entry ; MIPS-NEXT: $BB5_17:
; MIPS-NEXT: move $2, $25 ; MIPS-NEXT: beqz $13, $BB5_13
; MIPS-NEXT: $BB5_19: # %entry ; MIPS-NEXT: move $6, $25
; MIPS-NEXT: move $4, $6 ; MIPS-NEXT: $BB5_18:
; MIPS-NEXT: move $5, $7 ; MIPS-NEXT: bnez $14, $BB5_14
; MIPS-NEXT: lw $16, 0($sp) # 4-byte Folded Reload ; MIPS-NEXT: or $15, $10, $11
; MIPS-NEXT: lw $17, 4($sp) # 4-byte Folded Reload ; MIPS-NEXT: $BB5_19:
; MIPS-NEXT: jr $ra ; MIPS-NEXT: move $7, $15
; MIPS-NEXT: addiu $sp, $sp, 8 ; MIPS-NEXT: beqz $8, $BB5_15
; MIPS-NEXT: $BB5_20: # %entry ; MIPS-NEXT: srav $4, $4, $2
; MIPS-NEXT: srlv $1, $5, $25 ; MIPS-NEXT: $BB5_20:
; MIPS-NEXT: sllv $3, $17, $gp ; MIPS-NEXT: move $2, $9
; MIPS-NEXT: sltiu $gp, $25, 1 ; MIPS-NEXT: bnez $13, $BB5_22
; MIPS-NEXT: bnez $gp, $BB5_10 ; MIPS-NEXT: move $3, $4
; MIPS-NEXT: or $3, $3, $1 ; MIPS-NEXT: $BB5_21:
; MIPS-NEXT: $BB5_21: # %entry ; MIPS-NEXT: move $2, $9
; MIPS-NEXT: move $7, $16 ; MIPS-NEXT: $BB5_22:
; MIPS-NEXT: bnez $10, $BB5_11 ; MIPS-NEXT: bnez $13, $BB5_24
; MIPS-NEXT: sra $25, $4, 31
; MIPS-NEXT: $BB5_22: # %entry
; MIPS-NEXT: bnez $13, $BB5_12
; MIPS-NEXT: move $3, $25
; MIPS-NEXT: $BB5_23: # %entry
; MIPS-NEXT: not $1, $11
; MIPS-NEXT: srl $5, $5, 1
; MIPS-NEXT: sllv $4, $4, $11
; MIPS-NEXT: srlv $1, $5, $1
; MIPS-NEXT: bnez $8, $BB5_13
; MIPS-NEXT: or $9, $4, $1
; MIPS-NEXT: $BB5_24: # %entry
; MIPS-NEXT: move $2, $12
; MIPS-NEXT: bnez $24, $BB5_14
; MIPS-NEXT: move $4, $25
; MIPS-NEXT: $BB5_25: # %entry
; MIPS-NEXT: beqz $10, $BB5_15
; MIPS-NEXT: move $4, $14
; MIPS-NEXT: $BB5_26:
; MIPS-NEXT: bnez $gp, $BB5_16
; MIPS-NEXT: or $4, $2, $9
; MIPS-NEXT: $BB5_27: # %entry
; MIPS-NEXT: move $6, $4
; MIPS-NEXT: bnez $8, $BB5_17
; MIPS-NEXT: move $2, $25
; MIPS-NEXT: $BB5_28: # %entry
; MIPS-NEXT: bnez $10, $BB5_19
; MIPS-NEXT: move $2, $15
; MIPS-NEXT: # %bb.29: # %entry
; MIPS-NEXT: b $BB5_18
; MIPS-NEXT: nop ; MIPS-NEXT: nop
; MIPS-NEXT: # %bb.23:
; MIPS-NEXT: move $3, $9
; MIPS-NEXT: $BB5_24:
; MIPS-NEXT: move $4, $6
; MIPS-NEXT: jr $ra
; MIPS-NEXT: move $5, $7
; ;
; MIPS32-LABEL: ashr_i128: ; MIPS32-LABEL: ashr_i128:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
Context not available.
; ;
; MIPS3-LABEL: ashr_i128: ; MIPS3-LABEL: ashr_i128:
; MIPS3: # %bb.0: # %entry ; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: sll $8, $7, 0 ; MIPS3-NEXT: sll $2, $7, 0
; MIPS3-NEXT: dsrav $2, $4, $7 ; MIPS3-NEXT: andi $1, $2, 64
; MIPS3-NEXT: andi $6, $8, 64 ; MIPS3-NEXT: bnez $1, .LBB5_2
; MIPS3-NEXT: beqz $6, .LBB5_3 ; MIPS3-NEXT: dsrav $3, $4, $7
; MIPS3-NEXT: move $3, $2 ; MIPS3-NEXT: # %bb.1:
; MIPS3-NEXT: # %bb.1: # %entry
; MIPS3-NEXT: bnez $6, .LBB5_4
; MIPS3-NEXT: nop
; MIPS3-NEXT: .LBB5_2: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: nop
; MIPS3-NEXT: .LBB5_3: # %entry
; MIPS3-NEXT: dsrlv $1, $5, $7 ; MIPS3-NEXT: dsrlv $1, $5, $7
; MIPS3-NEXT: dsll $3, $4, 1 ; MIPS3-NEXT: dsll $4, $4, 1
; MIPS3-NEXT: not $5, $8 ; MIPS3-NEXT: not $2, $2
; MIPS3-NEXT: dsllv $3, $3, $5 ; MIPS3-NEXT: dsllv $2, $4, $2
; MIPS3-NEXT: beqz $6, .LBB5_2 ; MIPS3-NEXT: or $1, $2, $1
; MIPS3-NEXT: or $3, $3, $1 ; MIPS3-NEXT: move $2, $3
; MIPS3-NEXT: .LBB5_4: ; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: jr $ra ; MIPS3-NEXT: move $3, $1
; MIPS3-NEXT: dsra $2, $4, 63 ; MIPS3-NEXT: .LBB5_2:
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: dsra $2, $4, 63
; ;
; MIPS64-LABEL: ashr_i128: ; MIPS64-LABEL: ashr_i128:
; MIPS64: # %bb.0: # %entry ; MIPS64: # %bb.0: # %entry
Context not available.

test/CodeGen/Mips/llvm-ir/lshr.ll

Context not available.
define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
; MIPS2-LABEL: lshr_i64: ; MIPS2-LABEL: lshr_i64:
; MIPS2: # %bb.0: # %entry ; MIPS2: # %bb.0:
; MIPS2-NEXT: srlv $6, $4, $7 ; MIPS2-NEXT: srlv $6, $4, $7
; MIPS2-NEXT: andi $8, $7, 32 ; MIPS2-NEXT: andi $1, $7, 32
; MIPS2-NEXT: beqz $8, $BB4_3 ; MIPS2-NEXT: bnez $1, $BB4_2
; MIPS2-NEXT: move $3, $6
; MIPS2-NEXT: # %bb.1: # %entry
; MIPS2-NEXT: beqz $8, $BB4_4
; MIPS2-NEXT: addiu $2, $zero, 0 ; MIPS2-NEXT: addiu $2, $zero, 0
; MIPS2-NEXT: $BB4_2: # %entry ; MIPS2-NEXT: # %bb.1:
; MIPS2-NEXT: jr $ra ; MIPS2-NEXT: srlv $1, $5, $7
; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB4_3: # %entry
; MIPS2-NEXT: srlv $1, $5, $7
; MIPS2-NEXT: not $2, $7 ; MIPS2-NEXT: not $2, $7
; MIPS2-NEXT: sll $3, $4, 1 ; MIPS2-NEXT: sll $3, $4, 1
; MIPS2-NEXT: sllv $2, $3, $2 ; MIPS2-NEXT: sllv $2, $3, $2
; MIPS2-NEXT: or $3, $2, $1 ; MIPS2-NEXT: or $3, $2, $1
; MIPS2-NEXT: bnez $8, $BB4_2 ; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: addiu $2, $zero, 0 ; MIPS2-NEXT: move $2, $6
; MIPS2-NEXT: $BB4_4: # %entry ; MIPS2-NEXT: $BB4_2:
; MIPS2-NEXT: jr $ra ; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: move $2, $6 ; MIPS2-NEXT: move $3, $6
; ;
; MIPS32-LABEL: lshr_i64: ; MIPS32-LABEL: lshr_i64:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
Context not available.
define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MIPS2-LABEL: lshr_i128: ; MIPS2-LABEL: lshr_i128:
; MIPS2: # %bb.0: # %entry ; MIPS2: # %bb.0:
; MIPS2-NEXT: addiu $sp, $sp, -8 ; MIPS2-NEXT: lw $2, 28($sp)
; MIPS2-NEXT: .cfi_def_cfa_offset 8 ; MIPS2-NEXT: not $8, $2
; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill
; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill
; MIPS2-NEXT: .cfi_offset 17, -4
; MIPS2-NEXT: .cfi_offset 16, -8
; MIPS2-NEXT: lw $2, 36($sp)
; MIPS2-NEXT: addiu $1, $zero, 64 ; MIPS2-NEXT: addiu $1, $zero, 64
; MIPS2-NEXT: subu $10, $1, $2 ; MIPS2-NEXT: subu $11, $1, $2
; MIPS2-NEXT: sllv $9, $5, $10 ; MIPS2-NEXT: srlv $12, $6, $2
; MIPS2-NEXT: andi $13, $10, 32 ; MIPS2-NEXT: andi $9, $2, 32
; MIPS2-NEXT: addiu $8, $zero, 0 ; MIPS2-NEXT: bnez $9, $BB5_2
; MIPS2-NEXT: bnez $13, $BB5_2
; MIPS2-NEXT: addiu $25, $zero, 0
; MIPS2-NEXT: # %bb.1: # %entry
; MIPS2-NEXT: move $25, $9
; MIPS2-NEXT: $BB5_2: # %entry
; MIPS2-NEXT: not $3, $2
; MIPS2-NEXT: srlv $11, $6, $2
; MIPS2-NEXT: andi $12, $2, 32
; MIPS2-NEXT: bnez $12, $BB5_4
; MIPS2-NEXT: move $16, $11
; MIPS2-NEXT: # %bb.3: # %entry
; MIPS2-NEXT: srlv $1, $7, $2
; MIPS2-NEXT: sll $14, $6, 1
; MIPS2-NEXT: sllv $14, $14, $3
; MIPS2-NEXT: or $16, $14, $1
; MIPS2-NEXT: $BB5_4: # %entry
; MIPS2-NEXT: addiu $24, $2, -64
; MIPS2-NEXT: sll $17, $4, 1
; MIPS2-NEXT: srlv $14, $4, $24
; MIPS2-NEXT: andi $15, $24, 32
; MIPS2-NEXT: bnez $15, $BB5_6
; MIPS2-NEXT: move $gp, $14
; MIPS2-NEXT: # %bb.5: # %entry
; MIPS2-NEXT: srlv $1, $5, $24
; MIPS2-NEXT: not $24, $24
; MIPS2-NEXT: sllv $24, $17, $24
; MIPS2-NEXT: or $gp, $24, $1
; MIPS2-NEXT: $BB5_6: # %entry
; MIPS2-NEXT: sltiu $24, $2, 64
; MIPS2-NEXT: beqz $24, $BB5_8
; MIPS2-NEXT: nop
; MIPS2-NEXT: # %bb.7:
; MIPS2-NEXT: or $gp, $16, $25
; MIPS2-NEXT: $BB5_8: # %entry
; MIPS2-NEXT: srlv $25, $4, $2
; MIPS2-NEXT: bnez $12, $BB5_10
; MIPS2-NEXT: move $16, $25
; MIPS2-NEXT: # %bb.9: # %entry
; MIPS2-NEXT: srlv $1, $5, $2
; MIPS2-NEXT: sllv $3, $17, $3
; MIPS2-NEXT: or $16, $3, $1
; MIPS2-NEXT: $BB5_10: # %entry
; MIPS2-NEXT: bnez $12, $BB5_12
; MIPS2-NEXT: addiu $3, $zero, 0
; MIPS2-NEXT: # %bb.11: # %entry
; MIPS2-NEXT: move $3, $25
; MIPS2-NEXT: $BB5_12: # %entry
; MIPS2-NEXT: addiu $1, $zero, 63
; MIPS2-NEXT: sltiu $25, $2, 1
; MIPS2-NEXT: beqz $25, $BB5_22
; MIPS2-NEXT: sltu $17, $1, $2
; MIPS2-NEXT: # %bb.13: # %entry
; MIPS2-NEXT: beqz $17, $BB5_23
; MIPS2-NEXT: addiu $2, $zero, 0
; MIPS2-NEXT: $BB5_14: # %entry
; MIPS2-NEXT: beqz $17, $BB5_24
; MIPS2-NEXT: addiu $3, $zero, 0 ; MIPS2-NEXT: addiu $3, $zero, 0
; MIPS2-NEXT: $BB5_15: # %entry ; MIPS2-NEXT: # %bb.1: # %entry
; MIPS2-NEXT: beqz $13, $BB5_25 ; MIPS2-NEXT: srlv $1, $7, $2
; MIPS2-NEXT: sll $10, $6, 1
; MIPS2-NEXT: sllv $10, $10, $8
; MIPS2-NEXT: or $10, $10, $1
; MIPS2-NEXT: b $BB5_3
; MIPS2-NEXT: move $13, $12
; MIPS2-NEXT: $BB5_2:
; MIPS2-NEXT: addiu $13, $zero, 0
; MIPS2-NEXT: move $10, $12
; MIPS2-NEXT: $BB5_3: # %entry
; MIPS2-NEXT: andi $1, $11, 32
; MIPS2-NEXT: bnez $1, $BB5_5
; MIPS2-NEXT: sllv $12, $5, $11
; MIPS2-NEXT: # %bb.4: # %entry
; MIPS2-NEXT: sllv $1, $4, $11
; MIPS2-NEXT: not $11, $11
; MIPS2-NEXT: srl $14, $5, 1
; MIPS2-NEXT: srlv $11, $14, $11
; MIPS2-NEXT: b $BB5_6
; MIPS2-NEXT: or $15, $1, $11
; MIPS2-NEXT: $BB5_5:
; MIPS2-NEXT: move $15, $12
; MIPS2-NEXT: addiu $12, $zero, 0
; MIPS2-NEXT: $BB5_6: # %entry
; MIPS2-NEXT: addiu $14, $2, -64
; MIPS2-NEXT: sll $11, $4, 1
; MIPS2-NEXT: andi $1, $14, 32
; MIPS2-NEXT: bnez $1, $BB5_9
; MIPS2-NEXT: srlv $25, $4, $14
; MIPS2-NEXT: # %bb.7: # %entry
; MIPS2-NEXT: srlv $1, $5, $14
; MIPS2-NEXT: not $14, $14
; MIPS2-NEXT: sllv $14, $11, $14
; MIPS2-NEXT: move $24, $25
; MIPS2-NEXT: sltiu $25, $2, 64
; MIPS2-NEXT: beqz $25, $BB5_11
; MIPS2-NEXT: or $14, $14, $1
; MIPS2-NEXT: # %bb.8: # %entry
; MIPS2-NEXT: b $BB5_10
; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_9:
; MIPS2-NEXT: move $14, $25
; MIPS2-NEXT: sltiu $25, $2, 64
; MIPS2-NEXT: beqz $25, $BB5_11
; MIPS2-NEXT: addiu $24, $zero, 0
; MIPS2-NEXT: $BB5_10:
; MIPS2-NEXT: or $24, $13, $15
; MIPS2-NEXT: $BB5_11: # %entry
; MIPS2-NEXT: sltiu $13, $2, 1
; MIPS2-NEXT: beqz $13, $BB5_18
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_16: # %entry ; MIPS2-NEXT: # %bb.12: # %entry
; MIPS2-NEXT: beqz $12, $BB5_26 ; MIPS2-NEXT: bnez $25, $BB5_19
; MIPS2-NEXT: addiu $4, $zero, 0
; MIPS2-NEXT: $BB5_17: # %entry
; MIPS2-NEXT: beqz $15, $BB5_27
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_18: # %entry ; MIPS2-NEXT: $BB5_13: # %entry
; MIPS2-NEXT: bnez $24, $BB5_28 ; MIPS2-NEXT: bnez $13, $BB5_15
; MIPS2-NEXT: addiu $10, $zero, 63
; MIPS2-NEXT: $BB5_14: # %entry
; MIPS2-NEXT: move $7, $14
; MIPS2-NEXT: $BB5_15: # %entry
; MIPS2-NEXT: sltu $10, $10, $2
; MIPS2-NEXT: bnez $9, $BB5_21
; MIPS2-NEXT: srlv $12, $4, $2
; MIPS2-NEXT: # %bb.16: # %entry
; MIPS2-NEXT: srlv $1, $5, $2
; MIPS2-NEXT: sllv $2, $11, $8
; MIPS2-NEXT: or $4, $2, $1
; MIPS2-NEXT: move $5, $12
; MIPS2-NEXT: bnez $10, $BB5_23
; MIPS2-NEXT: addiu $2, $zero, 0
; MIPS2-NEXT: # %bb.17: # %entry
; MIPS2-NEXT: b $BB5_22
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_19: # %entry ; MIPS2-NEXT: $BB5_18: # %entry
; MIPS2-NEXT: bnez $25, $BB5_21 ; MIPS2-NEXT: beqz $25, $BB5_13
; MIPS2-NEXT: move $6, $24
; MIPS2-NEXT: $BB5_19:
; MIPS2-NEXT: or $14, $10, $12
; MIPS2-NEXT: bnez $13, $BB5_15
; MIPS2-NEXT: addiu $10, $zero, 63
; MIPS2-NEXT: # %bb.20:
; MIPS2-NEXT: b $BB5_14
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_20: # %entry ; MIPS2-NEXT: $BB5_21:
; MIPS2-NEXT: move $6, $8 ; MIPS2-NEXT: addiu $5, $zero, 0
; MIPS2-NEXT: $BB5_21: # %entry ; MIPS2-NEXT: move $4, $12
; MIPS2-NEXT: move $4, $6 ; MIPS2-NEXT: bnez $10, $BB5_23
; MIPS2-NEXT: move $5, $7
; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload
; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: addiu $sp, $sp, 8
; MIPS2-NEXT: $BB5_22: # %entry
; MIPS2-NEXT: move $7, $gp
; MIPS2-NEXT: bnez $17, $BB5_14
; MIPS2-NEXT: addiu $2, $zero, 0 ; MIPS2-NEXT: addiu $2, $zero, 0
; MIPS2-NEXT: $BB5_23: # %entry ; MIPS2-NEXT: $BB5_22: # %entry
; MIPS2-NEXT: move $2, $3 ; MIPS2-NEXT: move $2, $5
; MIPS2-NEXT: bnez $17, $BB5_15 ; MIPS2-NEXT: $BB5_23: # %entry
; MIPS2-NEXT: addiu $3, $zero, 0 ; MIPS2-NEXT: bnez $10, $BB5_25
; MIPS2-NEXT: $BB5_24: # %entry
; MIPS2-NEXT: bnez $13, $BB5_16
; MIPS2-NEXT: move $3, $16
; MIPS2-NEXT: $BB5_25: # %entry
; MIPS2-NEXT: not $1, $10
; MIPS2-NEXT: srl $5, $5, 1
; MIPS2-NEXT: sllv $4, $4, $10
; MIPS2-NEXT: srlv $1, $5, $1
; MIPS2-NEXT: or $9, $4, $1
; MIPS2-NEXT: bnez $12, $BB5_17
; MIPS2-NEXT: addiu $4, $zero, 0
; MIPS2-NEXT: $BB5_26: # %entry
; MIPS2-NEXT: bnez $15, $BB5_18
; MIPS2-NEXT: move $4, $11
; MIPS2-NEXT: $BB5_27: # %entry
; MIPS2-NEXT: beqz $24, $BB5_19
; MIPS2-NEXT: move $8, $14
; MIPS2-NEXT: $BB5_28:
; MIPS2-NEXT: bnez $25, $BB5_21
; MIPS2-NEXT: or $8, $4, $9
; MIPS2-NEXT: # %bb.29:
; MIPS2-NEXT: b $BB5_20
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: # %bb.24: # %entry
; MIPS2-NEXT: move $3, $4
; MIPS2-NEXT: $BB5_25: # %entry
; MIPS2-NEXT: move $4, $6
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: move $5, $7
; ;
; MIPS32-LABEL: lshr_i128: ; MIPS32-LABEL: lshr_i128:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
Context not available.
; MIPS32R6-NEXT: addiu $sp, $sp, 8 ; MIPS32R6-NEXT: addiu $sp, $sp, 8
; ;
; MIPS3-LABEL: lshr_i128: ; MIPS3-LABEL: lshr_i128:
; MIPS3: # %bb.0: # %entry ; MIPS3: # %bb.0:
; MIPS3-NEXT: sll $2, $7, 0 ; MIPS3-NEXT: sll $3, $7, 0
; MIPS3-NEXT: dsrlv $6, $4, $7 ; MIPS3-NEXT: dsrlv $6, $4, $7
; MIPS3-NEXT: andi $8, $2, 64 ; MIPS3-NEXT: andi $1, $3, 64
; MIPS3-NEXT: beqz $8, .LBB5_3 ; MIPS3-NEXT: bnez $1, .LBB5_2
; MIPS3-NEXT: move $3, $6 ; MIPS3-NEXT: daddiu $2, $zero, 0
; MIPS3-NEXT: # %bb.1: # %entry ; MIPS3-NEXT: # %bb.1: # %entry
; MIPS3-NEXT: beqz $8, .LBB5_4
; MIPS3-NEXT: daddiu $2, $zero, 0
; MIPS3-NEXT: .LBB5_2: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: nop
; MIPS3-NEXT: .LBB5_3: # %entry
; MIPS3-NEXT: dsrlv $1, $5, $7 ; MIPS3-NEXT: dsrlv $1, $5, $7
; MIPS3-NEXT: dsll $3, $4, 1 ; MIPS3-NEXT: dsll $2, $4, 1
; MIPS3-NEXT: not $2, $2 ; MIPS3-NEXT: not $3, $3
; MIPS3-NEXT: dsllv $2, $3, $2 ; MIPS3-NEXT: dsllv $2, $2, $3
; MIPS3-NEXT: or $3, $2, $1 ; MIPS3-NEXT: or $3, $2, $1
; MIPS3-NEXT: bnez $8, .LBB5_2 ; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: daddiu $2, $zero, 0 ; MIPS3-NEXT: move $2, $6
; MIPS3-NEXT: .LBB5_4: # %entry ; MIPS3-NEXT: .LBB5_2:
; MIPS3-NEXT: jr $ra ; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $2, $6 ; MIPS3-NEXT: move $3, $6
; ;
; MIPS4-LABEL: lshr_i128: ; MIPS4-LABEL: lshr_i128:
; MIPS4: # %bb.0: # %entry ; MIPS4: # %bb.0: # %entry
Context not available.

test/CodeGen/Mips/llvm-ir/shl.ll

Context not available.
define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
; MIPS2-LABEL: shl_i64: ; MIPS2-LABEL: shl_i64:
; MIPS2: # %bb.0: # %entry ; MIPS2: # %bb.0: # %entry
; MIPS2-NEXT: sllv $6, $5, $7 ; MIPS2-NEXT: andi $1, $7, 32
; MIPS2-NEXT: andi $8, $7, 32 ; MIPS2-NEXT: bnez $1, $BB4_2
; MIPS2-NEXT: beqz $8, $BB4_3 ; MIPS2-NEXT: sllv $3, $5, $7
; MIPS2-NEXT: move $2, $6 ; MIPS2-NEXT: # %bb.1:
; MIPS2-NEXT: # %bb.1: # %entry ; MIPS2-NEXT: sllv $1, $4, $7
; MIPS2-NEXT: beqz $8, $BB4_4
; MIPS2-NEXT: addiu $3, $zero, 0
; MIPS2-NEXT: $BB4_2: # %entry
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB4_3: # %entry
; MIPS2-NEXT: sllv $1, $4, $7
; MIPS2-NEXT: not $2, $7 ; MIPS2-NEXT: not $2, $7
; MIPS2-NEXT: srl $3, $5, 1 ; MIPS2-NEXT: srl $4, $5, 1
; MIPS2-NEXT: srlv $2, $3, $2 ; MIPS2-NEXT: srlv $2, $4, $2
; MIPS2-NEXT: or $2, $1, $2 ; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: bnez $8, $BB4_2 ; MIPS2-NEXT: or $2, $1, $2
; MIPS2-NEXT: $BB4_2:
; MIPS2-NEXT: move $2, $3
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: addiu $3, $zero, 0 ; MIPS2-NEXT: addiu $3, $zero, 0
; MIPS2-NEXT: $BB4_4: # %entry
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: move $3, $6
; ;
; MIPS32-LABEL: shl_i64: ; MIPS32-LABEL: shl_i64:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
Context not available.
define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
; MIPS2-LABEL: shl_i128: ; MIPS2-LABEL: shl_i128:
; MIPS2: # %bb.0: # %entry ; MIPS2: # %bb.0:
; MIPS2-NEXT: addiu $sp, $sp, -8 ; MIPS2-NEXT: lw $2, 28($sp)
; MIPS2-NEXT: .cfi_def_cfa_offset 8 ; MIPS2-NEXT: not $3, $2
; MIPS2-NEXT: sw $17, 4($sp) # 4-byte Folded Spill
; MIPS2-NEXT: sw $16, 0($sp) # 4-byte Folded Spill
; MIPS2-NEXT: .cfi_offset 17, -4
; MIPS2-NEXT: .cfi_offset 16, -8
; MIPS2-NEXT: lw $8, 36($sp)
; MIPS2-NEXT: addiu $1, $zero, 64 ; MIPS2-NEXT: addiu $1, $zero, 64
; MIPS2-NEXT: subu $10, $1, $8 ; MIPS2-NEXT: subu $11, $1, $2
; MIPS2-NEXT: srlv $3, $6, $10 ; MIPS2-NEXT: sllv $10, $5, $2
; MIPS2-NEXT: andi $13, $10, 32 ; MIPS2-NEXT: andi $9, $2, 32
; MIPS2-NEXT: addiu $2, $zero, 0 ; MIPS2-NEXT: bnez $9, $BB5_2
; MIPS2-NEXT: bnez $13, $BB5_2 ; MIPS2-NEXT: addiu $8, $zero, 0
; MIPS2-NEXT: addiu $25, $zero, 0 ; MIPS2-NEXT: # %bb.1:
; MIPS2-NEXT: # %bb.1: # %entry ; MIPS2-NEXT: sllv $1, $4, $2
; MIPS2-NEXT: move $25, $3 ; MIPS2-NEXT: srl $12, $5, 1
; MIPS2-NEXT: $BB5_2: # %entry ; MIPS2-NEXT: srlv $12, $12, $3
; MIPS2-NEXT: not $9, $8 ; MIPS2-NEXT: b $BB5_3
; MIPS2-NEXT: sllv $11, $5, $8 ; MIPS2-NEXT: or $12, $1, $12
; MIPS2-NEXT: andi $12, $8, 32 ; MIPS2-NEXT: $BB5_2:
; MIPS2-NEXT: bnez $12, $BB5_4 ; MIPS2-NEXT: move $12, $10
; MIPS2-NEXT: move $16, $11 ; MIPS2-NEXT: addiu $10, $zero, 0
; MIPS2-NEXT: # %bb.3: # %entry ; MIPS2-NEXT: $BB5_3:
; MIPS2-NEXT: sllv $1, $4, $8 ; MIPS2-NEXT: andi $1, $11, 32
; MIPS2-NEXT: srl $14, $5, 1 ; MIPS2-NEXT: bnez $1, $BB5_5
; MIPS2-NEXT: srlv $14, $14, $9 ; MIPS2-NEXT: srlv $14, $6, $11
; MIPS2-NEXT: or $16, $1, $14 ; MIPS2-NEXT: # %bb.4:
; MIPS2-NEXT: $BB5_4: # %entry ; MIPS2-NEXT: srlv $1, $7, $11
; MIPS2-NEXT: addiu $24, $8, -64 ; MIPS2-NEXT: not $11, $11
; MIPS2-NEXT: srl $17, $7, 1 ; MIPS2-NEXT: sll $13, $6, 1
; MIPS2-NEXT: sllv $14, $7, $24 ; MIPS2-NEXT: sllv $11, $13, $11
; MIPS2-NEXT: andi $15, $24, 32 ; MIPS2-NEXT: or $13, $11, $1
; MIPS2-NEXT: bnez $15, $BB5_6 ; MIPS2-NEXT: b $BB5_6
; MIPS2-NEXT: move $gp, $14 ; MIPS2-NEXT: move $15, $14
; MIPS2-NEXT: # %bb.5: # %entry ; MIPS2-NEXT: $BB5_5:
; MIPS2-NEXT: sllv $1, $6, $24 ; MIPS2-NEXT: addiu $15, $zero, 0
; MIPS2-NEXT: move $13, $14
; MIPS2-NEXT: $BB5_6:
; MIPS2-NEXT: addiu $24, $2, -64
; MIPS2-NEXT: srl $11, $7, 1
; MIPS2-NEXT: andi $1, $24, 32
; MIPS2-NEXT: bnez $1, $BB5_9
; MIPS2-NEXT: sllv $14, $7, $24
; MIPS2-NEXT: # %bb.7:
; MIPS2-NEXT: sllv $1, $6, $24
; MIPS2-NEXT: not $24, $24 ; MIPS2-NEXT: not $24, $24
; MIPS2-NEXT: srlv $24, $17, $24 ; MIPS2-NEXT: srlv $24, $11, $24
; MIPS2-NEXT: or $gp, $1, $24 ; MIPS2-NEXT: sltiu $25, $2, 64
; MIPS2-NEXT: $BB5_6: # %entry ; MIPS2-NEXT: beqz $25, $BB5_11
; MIPS2-NEXT: sltiu $24, $8, 64 ; MIPS2-NEXT: or $24, $1, $24
; MIPS2-NEXT: beqz $24, $BB5_8 ; MIPS2-NEXT: # %bb.8:
; MIPS2-NEXT: b $BB5_10
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: # %bb.7: ; MIPS2-NEXT: $BB5_9:
; MIPS2-NEXT: or $gp, $16, $25 ; MIPS2-NEXT: move $24, $14
; MIPS2-NEXT: $BB5_8: # %entry ; MIPS2-NEXT: sltiu $25, $2, 64
; MIPS2-NEXT: sllv $25, $7, $8 ; MIPS2-NEXT: beqz $25, $BB5_11
; MIPS2-NEXT: bnez $12, $BB5_10 ; MIPS2-NEXT: addiu $14, $zero, 0
; MIPS2-NEXT: move $16, $25 ; MIPS2-NEXT: $BB5_10:
; MIPS2-NEXT: # %bb.9: # %entry ; MIPS2-NEXT: or $24, $12, $15
; MIPS2-NEXT: sllv $1, $6, $8 ; MIPS2-NEXT: $BB5_11:
; MIPS2-NEXT: srlv $9, $17, $9 ; MIPS2-NEXT: sltiu $12, $2, 1
; MIPS2-NEXT: or $16, $1, $9 ; MIPS2-NEXT: beqz $12, $BB5_18
; MIPS2-NEXT: $BB5_10: # %entry
; MIPS2-NEXT: bnez $12, $BB5_12
; MIPS2-NEXT: addiu $9, $zero, 0
; MIPS2-NEXT: # %bb.11: # %entry
; MIPS2-NEXT: move $9, $25
; MIPS2-NEXT: $BB5_12: # %entry
; MIPS2-NEXT: addiu $1, $zero, 63
; MIPS2-NEXT: sltiu $25, $8, 1
; MIPS2-NEXT: beqz $25, $BB5_22
; MIPS2-NEXT: sltu $17, $1, $8
; MIPS2-NEXT: # %bb.13: # %entry
; MIPS2-NEXT: beqz $17, $BB5_23
; MIPS2-NEXT: addiu $8, $zero, 0
; MIPS2-NEXT: $BB5_14: # %entry
; MIPS2-NEXT: beqz $17, $BB5_24
; MIPS2-NEXT: addiu $9, $zero, 0
; MIPS2-NEXT: $BB5_15: # %entry
; MIPS2-NEXT: beqz $13, $BB5_25
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_16: # %entry ; MIPS2-NEXT: # %bb.12:
; MIPS2-NEXT: beqz $12, $BB5_26 ; MIPS2-NEXT: bnez $25, $BB5_19
; MIPS2-NEXT: addiu $6, $zero, 0
; MIPS2-NEXT: $BB5_17: # %entry
; MIPS2-NEXT: beqz $15, $BB5_27
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_18: # %entry ; MIPS2-NEXT: $BB5_13:
; MIPS2-NEXT: bnez $24, $BB5_28 ; MIPS2-NEXT: bnez $12, $BB5_15
; MIPS2-NEXT: addiu $10, $zero, 63
; MIPS2-NEXT: $BB5_14:
; MIPS2-NEXT: move $5, $14
; MIPS2-NEXT: $BB5_15:
; MIPS2-NEXT: sltu $10, $10, $2
; MIPS2-NEXT: bnez $9, $BB5_21
; MIPS2-NEXT: sllv $7, $7, $2
; MIPS2-NEXT: # %bb.16:
; MIPS2-NEXT: sllv $1, $6, $2
; MIPS2-NEXT: srlv $2, $11, $3
; MIPS2-NEXT: or $2, $1, $2
; MIPS2-NEXT: bnez $10, $BB5_23
; MIPS2-NEXT: addiu $6, $zero, 0
; MIPS2-NEXT: # %bb.17:
; MIPS2-NEXT: b $BB5_22
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_19: # %entry ; MIPS2-NEXT: $BB5_18:
; MIPS2-NEXT: bnez $25, $BB5_21 ; MIPS2-NEXT: beqz $25, $BB5_13
; MIPS2-NEXT: move $4, $24
; MIPS2-NEXT: $BB5_19:
; MIPS2-NEXT: or $14, $10, $13
; MIPS2-NEXT: bnez $12, $BB5_15
; MIPS2-NEXT: addiu $10, $zero, 63
; MIPS2-NEXT: # %bb.20:
; MIPS2-NEXT: b $BB5_14
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: $BB5_20: # %entry ; MIPS2-NEXT: $BB5_21:
; MIPS2-NEXT: move $5, $2 ; MIPS2-NEXT: move $2, $7
; MIPS2-NEXT: $BB5_21: # %entry ; MIPS2-NEXT: addiu $7, $zero, 0
; MIPS2-NEXT: move $2, $4 ; MIPS2-NEXT: bnez $10, $BB5_23
; MIPS2-NEXT: move $3, $5
; MIPS2-NEXT: move $4, $9
; MIPS2-NEXT: move $5, $8
; MIPS2-NEXT: lw $16, 0($sp) # 4-byte Folded Reload
; MIPS2-NEXT: lw $17, 4($sp) # 4-byte Folded Reload
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: addiu $sp, $sp, 8
; MIPS2-NEXT: $BB5_22: # %entry
; MIPS2-NEXT: move $4, $gp
; MIPS2-NEXT: bnez $17, $BB5_14
; MIPS2-NEXT: addiu $8, $zero, 0
; MIPS2-NEXT: $BB5_23: # %entry
; MIPS2-NEXT: move $8, $9
; MIPS2-NEXT: bnez $17, $BB5_15
; MIPS2-NEXT: addiu $9, $zero, 0
; MIPS2-NEXT: $BB5_24: # %entry
; MIPS2-NEXT: bnez $13, $BB5_16
; MIPS2-NEXT: move $9, $16
; MIPS2-NEXT: $BB5_25: # %entry
; MIPS2-NEXT: not $1, $10
; MIPS2-NEXT: sll $3, $6, 1
; MIPS2-NEXT: srlv $6, $7, $10
; MIPS2-NEXT: sllv $1, $3, $1
; MIPS2-NEXT: or $3, $1, $6
; MIPS2-NEXT: bnez $12, $BB5_17
; MIPS2-NEXT: addiu $6, $zero, 0 ; MIPS2-NEXT: addiu $6, $zero, 0
; MIPS2-NEXT: $BB5_26: # %entry ; MIPS2-NEXT: $BB5_22:
; MIPS2-NEXT: bnez $15, $BB5_18 ; MIPS2-NEXT: move $6, $2
; MIPS2-NEXT: move $6, $11 ; MIPS2-NEXT: $BB5_23:
; MIPS2-NEXT: $BB5_27: # %entry ; MIPS2-NEXT: bnez $10, $BB5_25
; MIPS2-NEXT: beqz $24, $BB5_19
; MIPS2-NEXT: move $2, $14
; MIPS2-NEXT: $BB5_28:
; MIPS2-NEXT: bnez $25, $BB5_21
; MIPS2-NEXT: or $2, $6, $3
; MIPS2-NEXT: # %bb.29:
; MIPS2-NEXT: b $BB5_20
; MIPS2-NEXT: nop ; MIPS2-NEXT: nop
; MIPS2-NEXT: # %bb.24:
; MIPS2-NEXT: move $8, $7
; MIPS2-NEXT: $BB5_25:
; MIPS2-NEXT: move $2, $4
; MIPS2-NEXT: move $3, $5
; MIPS2-NEXT: move $4, $6
; MIPS2-NEXT: jr $ra
; MIPS2-NEXT: move $5, $8
; ;
; MIPS32-LABEL: shl_i128: ; MIPS32-LABEL: shl_i128:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
Context not available.
; ;
; MIPS3-LABEL: shl_i128: ; MIPS3-LABEL: shl_i128:
; MIPS3: # %bb.0: # %entry ; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: sll $3, $7, 0 ; MIPS3-NEXT: sll $2, $7, 0
; MIPS3-NEXT: dsllv $6, $5, $7 ; MIPS3-NEXT: andi $1, $2, 64
; MIPS3-NEXT: andi $8, $3, 64 ; MIPS3-NEXT: bnez $1, .LBB5_2
; MIPS3-NEXT: beqz $8, .LBB5_3 ; MIPS3-NEXT: dsllv $3, $5, $7
; MIPS3-NEXT: move $2, $6 ; MIPS3-NEXT: # %bb.1:
; MIPS3-NEXT: # %bb.1: # %entry
; MIPS3-NEXT: beqz $8, .LBB5_4
; MIPS3-NEXT: daddiu $3, $zero, 0
; MIPS3-NEXT: .LBB5_2: # %entry
; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: nop
; MIPS3-NEXT: .LBB5_3: # %entry
; MIPS3-NEXT: dsllv $1, $4, $7 ; MIPS3-NEXT: dsllv $1, $4, $7
; MIPS3-NEXT: dsrl $2, $5, 1 ; MIPS3-NEXT: dsrl $4, $5, 1
; MIPS3-NEXT: not $3, $3 ; MIPS3-NEXT: not $2, $2
; MIPS3-NEXT: dsrlv $2, $2, $3 ; MIPS3-NEXT: dsrlv $2, $4, $2
; MIPS3-NEXT: or $2, $1, $2 ; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: bnez $8, .LBB5_2 ; MIPS3-NEXT: or $2, $1, $2
; MIPS3-NEXT: daddiu $3, $zero, 0 ; MIPS3-NEXT: .LBB5_2:
; MIPS3-NEXT: .LBB5_4: # %entry ; MIPS3-NEXT: move $2, $3
; MIPS3-NEXT: jr $ra ; MIPS3-NEXT: jr $ra
; MIPS3-NEXT: move $3, $6 ; MIPS3-NEXT: daddiu $3, $zero, 0
; ;
; MIPS4-LABEL: shl_i128: ; MIPS4-LABEL: shl_i128:
; MIPS4: # %bb.0: # %entry ; MIPS4: # %bb.0: # %entry
Context not available.