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[mips] Optimize shifts for types larger than GPR size (mips2/mips3)
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Authored by abeserminji on Jan 4 2019, 8:35 AM.

Details

Summary

With this patch, shifts are lowered to optimal number of instructions
necessary to shift types larger than the general purpose register size.

Diff Detail

Repository
rL LLVM

Event Timeline

abeserminji created this revision.Jan 4 2019, 8:35 AM

Update patch for context.

atanasyan accepted this revision.Jan 9 2019, 1:29 PM

LGTM with a couple of nits

lib/Target/Mips/MipsISelLowering.cpp
2443 ↗(On Diff #180828)

clang-format the if block please

4380 ↗(On Diff #180828)

s/instrution/instruction/

This revision is now accepted and ready to land.Jan 9 2019, 1:29 PM
abeserminji marked 2 inline comments as done.

Comments resolved.

This revision was automatically updated to reflect the committed changes.