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Differential D56310

GlobalISel: Implement widen for extract_vector_elt elt type
ClosedPublic

Authored by arsenm on Jan 4 2019, 12:01 AM.

Details

Reviewers
aemerson
dsanders
aditya_nandakumar
t.p.northover

Diff Detail

Event Timeline

arsenm created this revision.Jan 4 2019, 12:01 AM
Herald added subscribers: kristof.beyls, rovka, nhaehnle and 2 others. · View Herald TranscriptJan 4 2019, 12:01 AM
aemerson added inline comments.Jan 7 2019, 1:15 PM
test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
261

What are these comments for?

arsenm marked an inline comment as done.Jan 7 2019, 5:09 PM
arsenm added inline comments.
test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
261

These are cases that should be tested, but are broken for other reasons. I can remove them

arsenm updated this revision to Diff 180791.Jan 8 2019, 10:50 PM

Remove commented out test cases

aemerson accepted this revision.Jan 10 2019, 1:39 PM

LGTM.

This revision is now accepted and ready to land.Jan 10 2019, 1:39 PM
arsenm closed this revision.Jan 22 2019, 12:38 PM

r351871

Herald added a subscriber: volkan. · View Herald TranscriptJan 22 2019, 12:38 PM

Revision Contents

PathSize
lib/
CodeGen/
GlobalISel/
18 lines
Target/
AMDGPU/
19 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
98 lines

Diff 180791

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 996 Lines • ▼ Show 20 Lines case TargetOpcode::G_PHI: {
} }
MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock &MBB = *MI.getParent();
MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
case TargetOpcode::G_EXTRACT_VECTOR_ELT: case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
if (TypeIdx == 0) {
unsigned VecReg = MI.getOperand(1).getReg();
LLT VecTy = MRI.getType(VecReg);
Observer.changingInstr(MI);
widenScalarDst(MI, WideTy, 0);
widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
WideTy.getSizeInBits()),
1, TargetOpcode::G_SEXT);
Observer.changedInstr(MI);
return Legalized;
}
if (TypeIdx != 2) if (TypeIdx != 2)
return UnableToLegalize; return UnableToLegalize;
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
}
case TargetOpcode::G_FCEIL: case TargetOpcode::G_FCEIL:
if (TypeIdx != 0) if (TypeIdx != 0)
return UnableToLegalize; return UnableToLegalize;
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
▲ Show 20 Lines • Show All 418 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
// registers with scalar types. This means we can end up with // registers with scalar types. This means we can end up with
// G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
// operands. In assert builds, the instruction selector will assert // operands. In assert builds, the instruction selector will assert
// if it sees a generic instruction which isn't legal, so we need to // if it sees a generic instruction which isn't legal, so we need to
// tell it that scalar types are legal for pointer operands // tell it that scalar types are legal for pointer operands
setAction({G_GEP, S64}, Legal); setAction({G_GEP, S64}, Legal);
for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) { for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
unsigned VecTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 1 : 0;
unsigned EltTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 0 : 1;
unsigned IdxTypeIdx = 2;
getActionDefinitionsBuilder(Op) getActionDefinitionsBuilder(Op)
.legalIf([=](const LegalityQuery &Query) { .legalIf([=](const LegalityQuery &Query) {
const LLT &VecTy = Query.Types[1]; const LLT &VecTy = Query.Types[VecTypeIdx];
const LLT &IdxTy = Query.Types[2]; const LLT &IdxTy = Query.Types[IdxTypeIdx];
return VecTy.getSizeInBits() % 32 == 0 && return VecTy.getSizeInBits() % 32 == 0 &&
VecTy.getSizeInBits() <= 512 && VecTy.getSizeInBits() <= 512 &&
IdxTy.getSizeInBits() == 32; IdxTy.getSizeInBits() == 32;
}); })
.clampScalar(EltTypeIdx, S32, S64)
.clampScalar(VecTypeIdx, S32, S64)
.clampScalar(IdxTypeIdx, S32, S32);
} }
getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
.unsupportedIf([=](const LegalityQuery &Query) {
const LLT &EltTy = Query.Types[1].getElementType();
return Query.Types[0] != EltTy;
});
// FIXME: Doesn't handle extract of illegal sizes. // FIXME: Doesn't handle extract of illegal sizes.
getActionDefinitionsBuilder({G_EXTRACT, G_INSERT}) getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
.legalIf([=](const LegalityQuery &Query) { .legalIf([=](const LegalityQuery &Query) {
const LLT &Ty0 = Query.Types[0]; const LLT &Ty0 = Query.Types[0];
const LLT &Ty1 = Query.Types[1]; const LLT &Ty1 = Query.Types[1];
return (Ty0.getSizeInBits() % 32 == 0) && return (Ty0.getSizeInBits() % 32 == 0) &&
(Ty1.getSizeInBits() % 32 == 0); (Ty1.getSizeInBits() % 32 == 0);
}); });
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
--- ---
name: extract_vector_elt_0_v5i32 name: extract_vector_elt_0_v5i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v5i32 ; CHECK-LABEL: name: extract_vector_elt_0_v5i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<5 x s32>), [[C]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<5 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(<5 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0 %1:_(<5 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_0_v6i32 name: extract_vector_elt_0_v6i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v6i32 ; CHECK-LABEL: name: extract_vector_elt_0_v6i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<6 x s32>), [[C]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<6 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(<6 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0 %1:_(<6 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_0_v7i32 name: extract_vector_elt_0_v7i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v7i32 ; CHECK-LABEL: name: extract_vector_elt_0_v7i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<7 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<7 x s32>), [[C]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<7 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(<7 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0 %1:_(<7 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_0_v8i32 name: extract_vector_elt_0_v8i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v8i32 ; CHECK-LABEL: name: extract_vector_elt_0_v8i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<8 x s32>), [[C]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(<8 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0 %1:_(<8 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: extract_vector_elt_0_v16i32 name: extract_vector_elt_0_v16i32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v16i32 ; CHECK-LABEL: name: extract_vector_elt_0_v16i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<16 x s32>), [[C]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<16 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(<16 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0 %1:_(<16 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 25 Lines bb.0:
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32) ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32) ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 %0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s32) = COPY $vgpr2 %1:_(s32) = COPY $vgpr2
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
---
name: extract_vector_elt_0_v2i8_i32
body: |
bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %5(<2 x s32>), [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(<2 x s32>) = G_CONSTANT i64 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v2i16_i32
body: |
bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i16_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<2 x s16>), [[C]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(<2 x s16>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v2i1_i32
body: |
bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %5(<2 x s32>), [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(<2 x s32>) = G_CONSTANT i64 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v2i1_i1
body: |
bb.0:
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i32 0
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %5(<2 x s32>), [[SEXT]](s32)
; CHECK: [[C1:%[0-9]+]]:_(<2 x s32>) = G_CONSTANT i64 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_CONSTANT i32 0
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
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What are these comments for?

aemerson: What are these comments for?
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These are cases that should be tested, but are broken for other reasons. I can remove them

arsenm: These are cases that should be tested, but are broken for other reasons. I can remove them