[PowerPC] Fix assert from machine verify pass that atomic pseudo expanding causes mismatched register class

[• wuzish]

Summary

For atomic value operand which less than 4 bytes need to be masked.
And the related operation to calculate the newvalue can be done in 32 bit gprc.
So just use gprc for mask and value calculation.

[hfinkel]

Please fixup the comments, but LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

9982 ↗

(On Diff #179493)

This comment is wrapped oddly (you can go out to 80 characters), please rewrap. Also, it should end with a period.

10775 ↗

(On Diff #179493)

Same as above.

[• wuzish]

Address comment from reviewer.

[• wuzish]

The patch is out-of-date of trunk. Rebase to trunk.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
   F->insert(It, exitMBB);
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
   MachineRegisterInfo &RegInfo = F->getRegInfo();
   const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
                                           : &PPC::GPRCRegClass;
+  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
+
   unsigned PtrReg = RegInfo.createVirtualRegister(RC);
-  unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
+  unsigned Shift1Reg = RegInfo.createVirtualRegister(GPRC);
   unsigned ShiftReg =
-    isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
-  unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
-  unsigned MaskReg = RegInfo.createVirtualRegister(RC);
-  unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
-  unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
-  unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
-  unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
-  unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
-  unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
+    isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
+  unsigned Incr2Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned MaskReg = RegInfo.createVirtualRegister(GPRC);
+  unsigned Mask2Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned Mask3Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned Tmp3Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
+  unsigned TmpDestReg = RegInfo.createVirtualRegister(GPRC);
   unsigned Ptr1Reg;
-  unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
+  unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(GPRC);
+
+
 
   //  thisMBB:
   //   ...
   //   fallthrough --> loopMBB
   BB->addSuccessor(loopMBB);
 
   // The 4-byte load must be aligned, while a char or short may be
   // anywhere in the word.  Hence all this nasty bookkeeping code.
PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
   //   srw dest, tmpDest, shift
   if (ptrA != ZeroReg) {
     Ptr1Reg = RegInfo.createVirtualRegister(RC);
     BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
       .addReg(ptrA).addReg(ptrB);
   } else {
     Ptr1Reg = ptrB;
   }
-  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+  // We need use 32-bit subregister to avoid mismatch register class in 64-bit mode.
+  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
+      .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
       .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
   if (!isLittleEndian)
-    BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+    BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
         .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
   if (is64bit)
     BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
       .addReg(Ptr1Reg).addImm(0).addImm(61);
   else
     BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
       .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
   BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
       .addReg(incr).addReg(ShiftReg);
   if (is8bit)
     BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
   else {
     BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
     BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
   }
   BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
       .addReg(Mask2Reg).addReg(ShiftReg);
 
   BB = loopMBB;
   BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
     .addReg(ZeroReg).addReg(PtrReg);
   if (BinOpcode)
     BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
       .addReg(Incr2Reg).addReg(TmpDestReg);
-  BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
+  BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
     .addReg(TmpDestReg).addReg(MaskReg);
-  BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
+  BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg)
     .addReg(TmpReg).addReg(MaskReg);
   if (CmpOpcode) {
     // For unsigned comparisons, we can directly compare the shifted values.
     // For signed comparisons we shift and sign extend.
-    unsigned SReg = RegInfo.createVirtualRegister(RC);
-    BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), SReg)
+    unsigned SReg = RegInfo.createVirtualRegister(GPRC);
+    BuildMI(BB, dl, TII->get(PPC::AND), SReg)
       .addReg(TmpDestReg).addReg(MaskReg);
     unsigned ValueReg = SReg;
     unsigned CmpReg = Incr2Reg;
     if (CmpOpcode == PPC::CMPW) {
-      ValueReg = RegInfo.createVirtualRegister(RC);
+      ValueReg = RegInfo.createVirtualRegister(GPRC);
       BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
         .addReg(SReg).addReg(ShiftReg);
-      unsigned ValueSReg = RegInfo.createVirtualRegister(RC);
+      unsigned ValueSReg = RegInfo.createVirtualRegister(GPRC);
       BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
         .addReg(ValueReg);
       ValueReg = ValueSReg;
       CmpReg = incr;
     }
     BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
       .addReg(CmpReg).addReg(ValueReg);
     BuildMI(BB, dl, TII->get(PPC::BCC))
       .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
     BB->addSuccessor(loop2MBB);
     BB->addSuccessor(exitMBB);
     BB = loop2MBB;
   }
-  BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
+  BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg)
     .addReg(Tmp3Reg).addReg(Tmp2Reg);
   BuildMI(BB, dl, TII->get(PPC::STWCX))
     .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
   BuildMI(BB, dl, TII->get(PPC::BCC))
     .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
   BB->addSuccessor(loopMBB);
   BB->addSuccessor(exitMBB);
 
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     F->insert(It, exitMBB);
     exitMBB->splice(exitMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
                                             : &PPC::GPRCRegClass;
+    const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
+
     unsigned PtrReg = RegInfo.createVirtualRegister(RC);
-    unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
+    unsigned Shift1Reg = RegInfo.createVirtualRegister(GPRC);
     unsigned ShiftReg =
-      isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);
-    unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
-    unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
-    unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
-    unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
-    unsigned MaskReg = RegInfo.createVirtualRegister(RC);
-    unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
-    unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
-    unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
-    unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
-    unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
+      isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
+    unsigned NewVal2Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned NewVal3Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned OldVal2Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned OldVal3Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned MaskReg = RegInfo.createVirtualRegister(GPRC);
+    unsigned Mask2Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned Mask3Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
+    unsigned TmpDestReg = RegInfo.createVirtualRegister(GPRC);
     unsigned Ptr1Reg;
-    unsigned TmpReg = RegInfo.createVirtualRegister(RC);
+    unsigned TmpReg = RegInfo.createVirtualRegister(GPRC);
     unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
     //  thisMBB:
     //   ...
     //   fallthrough --> loopMBB
     BB->addSuccessor(loop1MBB);
 
     // The 4-byte load must be aligned, while a char or short may be
     // anywhere in the word.  Hence all this nasty bookkeeping code.
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     //   srw dest, tmpDest, shift
     if (ptrA != ZeroReg) {
       Ptr1Reg = RegInfo.createVirtualRegister(RC);
       BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
         .addReg(ptrA).addReg(ptrB);
     } else {
       Ptr1Reg = ptrB;
     }
-    BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+
+    // We need use 32-bit subregister to avoid mismatch register class in 64-bit mode.
+    BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
+        .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
         .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
     if (!isLittleEndian)
-      BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+      BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
           .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
     if (is64bit)
       BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
         .addReg(Ptr1Reg).addImm(0).addImm(61);
     else
       BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
         .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
     BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)

llvm/trunk/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Make sure that a negative value for the compare-and-swap is zero extended
 ; from i8/i16 to i32 since it will be compared for equality.
 ; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-P7
+; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P7
 
 @str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
 @str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
 @str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
 
 define signext i32 @main() {
 ; CHECK-LABEL: main:
 ; CHECK:    li 3, -32477

 ; CHECK-P7:    slw 8, 5, 3
 ; CHECK-P7:    slw 5, 7, 3
 ; CHECK-P7:    rldicr 4, 4, 0, 61
 ; CHECK-P7:    and 7, 6, 5
 ; CHECK-P7:    and 8, 8, 5
 ; CHECK-P7:  .LBB0_1: # %L.entry
 ; CHECK-P7:    lwarx 9, 0, 4
 ; CHECK-P7:    and 6, 9, 5
-; CHECK-P7:    cmpw 0, 6, 8
+; CHECK-P7:    cmpw 6, 8
 ; CHECK-P7:    bne 0, .LBB0_3
 ; CHECK-P7:    andc 9, 9, 5
 ; CHECK-P7:    or 9, 9, 7
 ; CHECK-P7:    stwcx. 9, 0, 4
 ; CHECK-P7:    bne 0, .LBB0_1
 ; CHECK-P7:    b .LBB0_4
 ; CHECK-P7:  .LBB0_3: # %L.entry
 ; CHECK-P7:    stwcx. 9, 0, 4

llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll

-; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
-; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
-; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
+; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr7 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add:
 ; CHECK: ldarx
   %tmp = atomicrmw add i64* %mem, i64 %val monotonic
 ; CHECK: stdcx.
   ret i64 %tmp
 }

llvm/trunk/test/CodeGen/PowerPC/atomic-minmax.ll

-; RUN: llc < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define void @a32min(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
 entry:
   %0 = atomicrmw min i32* %minimum, i32 %val monotonic
   ret void
 

 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
 ; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 0, 4, [[SESMOLDV]]
+; CHECK: cmpw 4, [[SESMOLDV]]
 ; CHECK: bgelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 

 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
 ; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 0, 4, [[SESMOLDV]]
+; CHECK: cmpw 4, [[SESMOLDV]]
 ; CHECK: blelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 
 define void @ae16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
 entry:
   %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
   ret void
 
 ; CHECK-LABEL: @ae16umin
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
 ; CHECK-DAG: rldicr 3, 3, 0, 61
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 0, 4, [[MOLDV]]
+; CHECK: cmplw 4, [[MOLDV]]
 ; CHECK: bgelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 
 define void @ae16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
 entry:
   %0 = atomicrmw umax i16* %minimum, i16 %val monotonic
   ret void
 
 ; CHECK-LABEL: @ae16umax
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
 ; CHECK-DAG: rldicr 3, 3, 0, 61
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 0, 4, [[MOLDV]]
+; CHECK: cmplw 4, [[MOLDV]]
 ; CHECK: blelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 

 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
 ; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 0, 4, [[SESMOLDV]]
+; CHECK: cmpw 4, [[SESMOLDV]]
 ; CHECK: bgelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 

 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
 ; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 0, 4, [[SESMOLDV]]
+; CHECK: cmpw 4, [[SESMOLDV]]
 ; CHECK: blelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 
 define void @ae8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
 entry:
   %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
   ret void
 
 ; CHECK-LABEL: @ae8umin
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
 ; CHECK-DAG: rldicr 3, 3, 0, 61
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 0, 4, [[MOLDV]]
+; CHECK: cmplw 4, [[MOLDV]]
 ; CHECK: bgelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 
 define void @ae8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
 entry:
   %0 = atomicrmw umax i8* %minimum, i8 %val monotonic
   ret void
 
 ; CHECK-LABEL: @ae8umax
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
 ; CHECK-DAG: rldicr 3, 3, 0, 61
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
 ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
 ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 0, 4, [[MOLDV]]
+; CHECK: cmplw 4, [[MOLDV]]
 ; CHECK: blelr 0
 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
 ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
 ; CHECK: stwcx. [[NEWV]], 0, 3
 ; CHECK: bne  0,
 ; CHECK: blr
 }
 
 attributes #0 = { nounwind "target-cpu"="ppc64" }
 attributes #1 = { nounwind "target-cpu"="pwr8" }
 

llvm/trunk/test/CodeGen/PowerPC/atomics.ll

-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs  -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
-; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs  -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
 ; This is already checked for in Atomics-64.ll
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu  -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu  -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
 
 ; FIXME: we don't currently check for the operations themselves with CHECK-NEXT,
 ;   because they are implemented in a very messy way with lwarx/stwcx.
 ;   It should be fixed soon in another patch.
 
 ; We first check loads, for all sizes from i8 to i64.
 ; We also vary orderings to check for barriers.
 define i8 @load_i8_unordered(i8* %mem) {