[ARM] Add missing patterns for DSP muls

[samparker]

Summary

Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands allow with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth.

[efriedma]

lib/Target/ARM/ARMInstrThumb2.td

2754

Does ISel automatically match the commuted version? (IIRC it does, but I haven't looked in a while.)

Could you use "PatFrags" to make a pattern that's either a sext_inreg or a sext_16_node, so you don't have to repeat these patterns? I haven't actually tried something like that, but I think it's possible.

[samparker]

Hi Eli,

Thanks for taking a look. Yes, the operands can be commuted and it's why the tests accept top-bottom and bottom-top muls in those tests. I've now also added a few extra tests with swapped operands.

I've tried to combine these patterns before into something nicer, without luck and again I've tried and failed... The errors given by tablegen leave me baffled: I seem to be hitting a problem using 'PatFrags' matching a 'PatFrag' and a 'PatLeaf' and also some kind of type errors that I haven't seen before! However, I have created some PatFrags for the muls to simplify the descriptions.

[efriedma]

LGTM

lib/Target/ARM/ARMInstrInfo.td

 
 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
 def imm16_31 : ImmLeaf<i32, [{
   return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
 }]>;
 
 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
-  if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17)
-    return true;
-
-  if (N->getOpcode() != ISD::SRA)
-    return false;
-  if (N->getOperand(0).getOpcode() != ISD::SHL)
-    return false;
-
-  auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  if (!ShiftVal || ShiftVal->getZExtValue() != 16)
-    return false;
-
-  ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1));
-  if (!ShiftVal || ShiftVal->getZExtValue() != 16)
-    return false;
-
-  return true;
+  return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
 }]>;
 
 /// Split a 32-bit immediate into two 16 bit parts.
 def hi16 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
                                    MVT::i32);
 }]>;
 

 
 def : ARMPat<(extloadi8  addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
 
 // smul* and smla*
 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
                  (SMULBB GPR:$a, GPR:$b)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+def : ARMV5TEPat<(mul sext_16_node:$a, (sext_inreg GPR:$b, i16)),
+                 (SMULBB GPR:$a, GPR:$b)>,
+      Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
                  (SMULBT GPR:$a, GPR:$b)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
                 (SMULTB GPR:$a, GPR:$b)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 def : ARMV5MOPat<(add GPR:$acc,
                       (mul sext_16_node:$a, sext_16_node:$b)),
                  (SMLABB GPR:$a, GPR:$b, GPR:$acc)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 def : ARMV5MOPat<(add GPR:$acc,
+                      (mul sext_16_node:$a, (sext_inreg GPR:$b, i16))),
+                 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>,
+      Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
+def : ARMV5MOPat<(add GPR:$acc,
                       (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
                  (SMLABT GPR:$a, GPR:$b, GPR:$acc)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 def : ARMV5MOPat<(add GPR:$acc,
                       (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
                  (SMLATB GPR:$a, GPR:$b, GPR:$acc)>,
       Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
 

lib/Target/ARM/ARMInstrThumb2.td

                                    (sra rGPR:$Rm, (i32 16))))]>;
 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
              [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
              [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
 
 def : Thumb2DSPPat<(mul sext_16_node:$Rm, sext_16_node:$Rn),
                    (t2SMULBB rGPR:$Rm, rGPR:$Rn)>;
+def : Thumb2DSPPat<(mul sext_16_node:$Rm, (sext_inreg rGPR:$Rn, i16)),
+                   (t2SMULBB rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16))),
                    (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
 def : Thumb2DSPPat<(mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm),
                    (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
 def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm),
                    (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;
 def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm),
                    (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;

                                                  (sra rGPR:$Rm, (i32 16)))))]>;
 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
              [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
              [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
 
 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
                       (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
+def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
+                                          (sext_inreg rGPR:$Rm, i16))),
+                      (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
 def : Thumb2DSPMulPat<(add rGPR:$Ra,
                         (mul sext_16_node:$Rn, (sra rGPR:$Rm, (i32 16)))),
                       (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
 def : Thumb2DSPMulPat<(add rGPR:$Ra,
                         (mul (sra rGPR:$Rn, (i32 16)), sext_16_node:$Rm)),
                       (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
 
 def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),

test/CodeGen/ARM/smul.ll

; CHECK-THUMBV6-NOT: smulbb
         %tmp1 = sext i16 %x to i32
         %tmp2 = sext i16 %x to i32
         %tmp3 = mul i32 %tmp1, %tmp2
         ret i32 %tmp3
 }
 
 define i32 @f17(i32 %x, i32 %y) {
 ; CHECK-LABEL: f17:
+; CHECK-NOT: sxth
 ; CHECK: smulbb
 ; CHECK-THUMBV6-NOT: smulbb
         %tmp1 = shl i32 %x, 16
         %tmp2 = shl i32 %y, 16
         %tmp3 = ashr i32 %tmp1, 16
         %tmp4 = ashr i32 %tmp2, 16
         %tmp5 = mul i32 %tmp3, %tmp4
         ret i32 %tmp5
 }
 
 define i32 @f18(i32 %a, i32 %x, i32 %y) {
 ; CHECK-LABEL: f18:
+; CHECK-NOT: sxth
 ; CHECK: {{smlabt r0, r1, r2, r0|smlatb r0, r2, r1, r0}}
 ; CHECK-THUMBV6-NOT: {{smlabt|smlatb}}
         %tmp0 = shl i32 %x, 16
         %tmp1 = ashr i32 %tmp0, 16
         %tmp2 = ashr i32 %y, 16
         %tmp3 = mul i32 %tmp2, %tmp1
         %tmp5 = add i32 %tmp3, %a
         ret i32 %tmp5
 }
 
 define i32 @f19(i32 %a, i32 %x, i32 %y) {
 ; CHECK-LABEL: f19:
 ; CHECK: {{smlatb r0, r1, r2, r0|smlabt r0, r2, r1, r0}}
 ; CHECK-THUMBV6-NOT: {{smlatb|smlabt}}
         %tmp0 = shl i32 %y, 16
         %tmp1 = ashr i32 %tmp0, 16
         %tmp2 = ashr i32 %x, 16
         %tmp3 = mul i32 %tmp2, %tmp1
         %tmp5 = add i32 %tmp3, %a
         ret i32 %tmp5
 }
 
 define i32 @f20(i32 %a, i32 %x, i32 %y) {
 ; CHECK-LABEL: f20:
+; CHECK-NOT: sxth
 ; CHECK: smlabb
 ; CHECK-THUMBV6-NOT: smlabb
         %tmp1 = shl i32 %x, 16
         %tmp2 = ashr i32 %tmp1, 16
         %tmp3 = shl i32 %y, 16
         %tmp4 = ashr i32 %tmp3, 16
         %tmp5 = mul i32 %tmp2, %tmp4
         %tmp6 = add i32 %tmp5, %a
; CHECK-THUMBV6-NOT: smlabb
         %tmp5 = add i32 %a, %tmp4
         ret i32 %tmp5
 }
 
 @global_b = external global i16, align 2
 
 define i32 @f22(i32 %a) {
 ; CHECK-LABEL: f22:
+; CHECK-NOT: sxth
 ; CHECK: smulwb r0, r0, r1
 ; CHECK-THUMBV6-NOT: smulwb
         %b = load i16, i16* @global_b, align 2
         %sext = sext i16 %b to i64
         %conv = sext i32 %a to i64
         %mul = mul nsw i64 %sext, %conv
         %shr37 = lshr i64 %mul, 16
         %conv4 = trunc i64 %shr37 to i32
         ret i32 %conv4
 }
 
 define i32 @f23(i32 %a, i32 %c) {
 ; CHECK-LABEL: f23:
+; CHECK-NOT: sxth
 ; CHECK: smlawb r0, r0, r2, r1
 ; CHECK-THUMBV6-NOT: smlawb
         %b = load i16, i16* @global_b, align 2
         %sext = sext i16 %b to i64
         %conv = sext i32 %a to i64
         %mul = mul nsw i64 %sext, %conv
         %shr49 = lshr i64 %mul, 16
         %conv5 = trunc i64 %shr49 to i32
         %add = add nsw i32 %conv5, %c
         ret i32 %add
 }
+
+; CHECK-LABEL: f24
+; CHECK-NOT: sxth
+; CHECK: smulbb
+define i32 @f24(i16* %a, i32* %b, i32* %c) {
+  %ld.0 = load i16, i16* %a, align 2
+  %ld.1 = load i32, i32* %b, align 4
+  %conv.0 = sext i16 %ld.0 to i32
+  %shift = shl i32 %ld.1, 16
+  %conv.1 = ashr i32 %shift, 16
+  %mul.0 = mul i32 %conv.0, %conv.1
+  store i32 %ld.1, i32* %c
+  ret i32 %mul.0
+}
+
+; CHECK-LABEL: f25
+; CHECK-NOT: sxth
+; CHECK: smulbb
+define i32 @f25(i16* %a, i32 %b, i32* %c) {
+  %ld.0 = load i16, i16* %a, align 2
+  %conv.0 = sext i16 %ld.0 to i32
+  %shift = shl i32 %b, 16
+  %conv.1 = ashr i32 %shift, 16
+  %mul.0 = mul i32 %conv.0, %conv.1
+  store i32 %b, i32* %c
+  ret i32 %mul.0
+}
+
+; CHECK-LABEL: f26
+; CHECK-NOT: sxth
+; CHECK: {{smulbt | smultb }}
+define i32 @f26(i16* %a, i32 %b, i32* %c) {
+  %ld.0 = load i16, i16* %a, align 2
+  %conv.0 = sext i16 %ld.0 to i32
+  %conv.1 = ashr i32 %b, 16
+  %mul.0 = mul i32 %conv.0, %conv.1
+  store i32 %b, i32* %c
+  ret i32 %mul.0
+}
+
+; CHECK-LABEL: f27
+; CHECK-NOT: sxth
+; CHECK: smulbb
+; CHECK: {{smlabt | smlatb }}
+define i32 @f27(i16* %a, i32* %b) {
+  %ld.0 = load i16, i16* %a, align 2
+  %ld.1 = load i32, i32* %b, align 4
+  %conv.0 = sext i16 %ld.0 to i32
+  %shift = shl i32 %ld.1, 16
+  %conv.1 = ashr i32 %shift, 16
+  %conv.2 = ashr i32 %ld.1, 16
+  %mul.0 = mul i32 %conv.0, %conv.1
+  %mul.1 = mul i32 %conv.0, %conv.2
+  %add = add i32 %mul.0, %mul.1
+  ret i32 %add
+}
+
+; CHECK-LABEL: f28
+; CHECK-NOT: sxth
+; CHECK: smulbb
+; CHECK: {{smlabt | smlatb }}
+define i32 @f28(i16* %a, i32* %b) {
+  %ld.0 = load i16, i16* %a, align 2
+  %ld.1 = load i32, i32* %b, align 4
+  %conv.0 = sext i16 %ld.0 to i32
+  %shift = shl i32 %ld.1, 16
+  %conv.1 = ashr i32 %shift, 16
+  %conv.2 = ashr i32 %ld.1, 16
+  %mul.0 = mul i32 %conv.0, %conv.1
+  %mul.1 = mul i32 %conv.2, %conv.0
+  %add = add i32 %mul.0, %mul.1
+  ret i32 %add
+}
+