[WebAssembly] Emit a splat for v128 IMPLICIT_DEF

[tlively]

Summary

This is a code size savings and is also important to get runnable code
while engines do not support v128.const.

[aheejin]

• So your intention was to do this even after we support v128.const, because it is code size savings, right?
• So there were no assumptions broken after we insert a new instruction after stackification?

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

130 ↗

(On Diff #179003)

There is a version of BuildMI that takes an instruction before which a new instruction is inserted. With this you don't need to insert it explicitly after creation.

[tlively]

• Use BuildMI that inserts instruction

[tlively]

In D55910#1337120, @aheejin wrote:

• So your intention was to do this even after we support v128.const, because it is code size savings, right?

That's right. V8 not supporting v128.const just made it a little more urgent.

• So there were no assumptions broken after we insert a new instruction after stackification?

Looks like it worked out. The insertion is a local, type-safe change that happens before the registers are stripped and the opcodes changed to their stack forms, so it seems ok.

[aheejin]

LGTM with a nit.

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

129 ↗

(On Diff #179008)

You don't need .getInstr(); MachineInstrBuilder has a conversion operator to MachineInstr *.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
                                              /*isImp=*/true));
 }
 
 // Convert an IMPLICIT_DEF instruction into an instruction which defines
 // a constant zero value.
 static void ConvertImplicitDefToConstZero(MachineInstr *MI,
                                           MachineRegisterInfo &MRI,
                                           const TargetInstrInfo *TII,
-                                          MachineFunction &MF) {
+                                          MachineFunction &MF,
+                                          LiveIntervals &LIS) {
   assert(MI->getOpcode() == TargetOpcode::IMPLICIT_DEF);
 
   const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
   if (RegClass == &WebAssembly::I32RegClass) {
     MI->setDesc(TII->get(WebAssembly::CONST_I32));
     MI->addOperand(MachineOperand::CreateImm(0));
   } else if (RegClass == &WebAssembly::I64RegClass) {
     MI->setDesc(TII->get(WebAssembly::CONST_I64));
     MI->addOperand(MachineOperand::CreateImm(0));
   } else if (RegClass == &WebAssembly::F32RegClass) {
     MI->setDesc(TII->get(WebAssembly::CONST_F32));
     ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue(
         Type::getFloatTy(MF.getFunction().getContext())));
     MI->addOperand(MachineOperand::CreateFPImm(Val));
   } else if (RegClass == &WebAssembly::F64RegClass) {
     MI->setDesc(TII->get(WebAssembly::CONST_F64));
     ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue(
         Type::getDoubleTy(MF.getFunction().getContext())));
     MI->addOperand(MachineOperand::CreateFPImm(Val));
   } else if (RegClass == &WebAssembly::V128RegClass) {
-    // TODO: make splat instead of constant
-    MI->setDesc(TII->get(WebAssembly::CONST_V128_v16i8));
-    for (int I = 0; I < 16; ++I)
-      MI->addOperand(MachineOperand::CreateImm(0));
+    unsigned TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
+    MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
+    MI->addOperand(MachineOperand::CreateReg(TempReg, false));
+    MachineInstr *Const = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
+                                  TII->get(WebAssembly::CONST_I32), TempReg)
+                              .addImm(0);
+    LIS.InsertMachineInstrInMaps(*Const);
   } else {
     llvm_unreachable("Unexpected reg class");
   }
 }
 
 // Determine whether a call to the callee referenced by
 // MI->getOperand(CalleeOpNo) reads memory, writes memory, and/or has side
 // effects.
for (auto MII = MBB.rbegin(); MII != MBB.rend(); ++MII) {
           // Proceed to the next operand.
           continue;
         }
 
         // If the instruction we just stackified is an IMPLICIT_DEF, convert it
         // to a constant 0 so that the def is explicit, and the push/pop
         // correspondence is maintained.
         if (Insert->getOpcode() == TargetOpcode::IMPLICIT_DEF)
-          ConvertImplicitDefToConstZero(Insert, MRI, TII, MF);
+          ConvertImplicitDefToConstZero(Insert, MRI, TII, MF, LIS);
 
         // We stackified an operand. Add the defining instruction's operands to
         // the worklist stack now to continue to build an ever deeper tree.
         Commuting.Reset();
         TreeWalker.PushOperands(Insert);
       }
 
       // If we stackified any operands, skip over the tree to start looking for

llvm/trunk/test/CodeGen/WebAssembly/implicit-def.ll

 X:                                                ; preds = %0, C
   %i = phi double [ 1.0, %0 ], [ %h, %C ]
   ret double %i
 }
 
 ; CHECK-LABEL: implicit_def_v4i32:
 ; CHECK: .LBB{{[0-9]+}}_4:{{$}}
 ; CHECK-NEXT: end_block{{$}}
-; CHECK-NEXT: v128.const $push[[R:[0-9]+]]=, 0, 0, 0, 0, 0, 0, 0, 0,
-; CHECK-SAME:                                0, 0, 0, 0, 0, 0, 0, 0{{$}}
+; CHECK-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK-NEXT: i32x4.splat $push[[R:[0-9]+]]=, $pop[[L0]]
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 ; CHECK-NEXT: end_function{{$}}
 define <4 x i32> @implicit_def_v4i32() {
   br i1 undef, label %A, label %X
 
 A:                                                ; preds = %0
   %d = icmp slt i1 0, 0
   br i1 %d, label %C, label %B