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Differential D55753

AMDGPU/GlobalISel: RegBankSelect for carry-in
ClosedPublic

Authored by arsenm on Dec 16 2018, 4:43 PM.

Details

Reviewers
tstellar
rampitec
Summary

I'm not sure we should be allowing the truncate
to s1 for the inputs. It may be necessary to
create a new VCC reg bank.

Diff Detail

Event Timeline

arsenm created this revision.Dec 16 2018, 4:43 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptDec 16 2018, 4:43 PM
arsenm added a reviewer: rampitec.Jan 21 2019, 2:54 PM
Herald added a subscriber: volkan. · View Herald TranscriptJan 21 2019, 2:54 PM
arsenm added a comment.Jan 21 2019, 2:54 PM

ping

tstellar accepted this revision.Jan 22 2019, 1:44 PM

LGTM.

This revision is now accepted and ready to land.Jan 22 2019, 1:44 PM
arsenm closed this revision.Jan 22 2019, 1:46 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
33 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
149 lines
149 lines
148 lines
149 lines

Diff 178416

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
setAction({G_ADD, S32}, Legal); setAction({G_ADD, S32}, Legal);
setAction({G_SUB, S32}, Legal); setAction({G_SUB, S32}, Legal);
setAction({G_MUL, S32}, Legal); setAction({G_MUL, S32}, Legal);
setAction({G_AND, S32}, Legal); setAction({G_AND, S32}, Legal);
setAction({G_OR, S32}, Legal); setAction({G_OR, S32}, Legal);
setAction({G_XOR, S32}, Legal); setAction({G_XOR, S32}, Legal);
getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO}) getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
.legalFor({{S32, S1}}); .legalFor({{S32, S1}});
setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, V2S16}, Legal);
setAction({G_BITCAST, 1, S32}, Legal); setAction({G_BITCAST, 1, S32}, Legal);
setAction({G_BITCAST, S32}, Legal); setAction({G_BITCAST, S32}, Legal);
setAction({G_BITCAST, 1, V2S16}, Legal); setAction({G_BITCAST, 1, V2S16}, Legal);
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}), AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands 4); // Num Operands
AltMappings.push_back(&VVMapping); AltMappings.push_back(&VVMapping);
return AltMappings; return AltMappings;
} }
case TargetOpcode::G_UADDE:
case TargetOpcode::G_USUBE:
case TargetOpcode::G_SADDE:
case TargetOpcode::G_SSUBE: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}),
5); // Num Operands
AltMappings.push_back(&SSMapping);
const InstructionMapping &VVMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}),
5); // Num Operands
AltMappings.push_back(&VVMapping);
return AltMappings;
}
default: default:
break; break;
} }
return RegisterBankInfo::getInstrAlternativeMappings(MI); return RegisterBankInfo::getInstrAlternativeMappings(MI);
} }
void AMDGPURegisterBankInfo::applyMappingImpl( void AMDGPURegisterBankInfo::applyMappingImpl(
const OperandsMapper &OpdMapper) const { const OperandsMapper &OpdMapper) const {
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
unsigned DefaultBankID = Size1 == 1 ? unsigned DefaultBankID = Size1 == 1 ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID); unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI, DefaultBankID);
OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1); OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) { for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); unsigned BankID = Size == 1 ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(BankID, Size);
} }
return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping), return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
MI.getNumOperands()); MI.getNumOperands());
} }
const RegisterBankInfo::InstructionMapping & const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const { AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_XOR: case AMDGPU::G_XOR:
case AMDGPU::G_SHL: case AMDGPU::G_SHL:
case AMDGPU::G_LSHR: case AMDGPU::G_LSHR:
case AMDGPU::G_ASHR: case AMDGPU::G_ASHR:
case AMDGPU::G_UADDO: case AMDGPU::G_UADDO:
case AMDGPU::G_SADDO: case AMDGPU::G_SADDO:
case AMDGPU::G_USUBO: case AMDGPU::G_USUBO:
case AMDGPU::G_SSUBO: case AMDGPU::G_SSUBO:
case AMDGPU::G_UADDE:
case AMDGPU::G_SADDE:
case AMDGPU::G_USUBE:
case AMDGPU::G_SSUBE:
if (isSALUMapping(MI)) if (isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AMDGPU::G_FADD: case AMDGPU::G_FADD:
case AMDGPU::G_FSUB: case AMDGPU::G_FSUB:
case AMDGPU::G_FPTOSI: case AMDGPU::G_FPTOSI:
case AMDGPU::G_FPTOUI: case AMDGPU::G_FPTOUI:
▲ Show 20 Lines • Show All 283 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
---
name: sadde_s32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: sadde_s32_sss
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
; GREEDY-LABEL: name: sadde_s32_sss
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
...
---
name: sadde_s32_vss
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: sadde_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: sadde_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
...
---
name: sadde_s32_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: sadde_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: sadde_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...
---
name: sadde_s32_vvs
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: sadde_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]
; GREEDY-LABEL: name: sadde_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY]], [[COPY1]], [[TRUNC]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...
---
name: sadde_s32_sss_noscc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: sadde_s32_sss_noscc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: sadde_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[TRUNC]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SADDE %0, %1, %3
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
---
name: ssube_s32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: ssube_s32_sss
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
; GREEDY-LABEL: name: ssube_s32_sss
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
...
---
name: ssube_s32_vss
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: ssube_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: ssube_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
...
---
name: ssube_s32_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: ssube_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: ssube_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...
---
name: ssube_s32_vvs
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: ssube_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]
; GREEDY-LABEL: name: ssube_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY]], [[COPY1]], [[TRUNC]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...
---
name: ssubee_s32_sss_noscc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: ssubee_s32_sss_noscc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: ssubee_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[TRUNC]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_SSUBE %0, %1, %3
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
---
name: uadde_s32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: uadde_s32_sss
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
; GREEDY-LABEL: name: uadde_s32_sss
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
...
---
name: uadde_s32_vss
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: uadde_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: uadde_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
...
---
name: uadde_s32_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: uadde_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: uadde_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...
---
name: uadde_s32_vvs
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: uadde_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
; GREEDY-LABEL: name: uadde_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...
---
name: uadde_s32_sss_noscc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: uadde_s32_sss_noscc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: uadde_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[TRUNC]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
---
name: usube_s32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: usube_s32_sss
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
; GREEDY-LABEL: name: usube_s32_sss
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
...
---
name: usube_s32_vss
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0, $sgpr1
; FAST-LABEL: name: usube_s32_vss
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
; GREEDY-LABEL: name: usube_s32_vss
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY3]], [[COPY4]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(s32) = G_CONSTANT i64 0
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
...
---
name: usube_s32_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0
; FAST-LABEL: name: usube_s32_ssv
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]]
; GREEDY-LABEL: name: usube_s32_ssv
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...
---
name: usube_s32_vvs
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0
; FAST-LABEL: name: usube_s32_vvs
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]
; GREEDY-LABEL: name: usube_s32_vvs
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY]], [[COPY1]], [[TRUNC]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...
---
name: usube_s32_sss_noscc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; FAST-LABEL: name: usube_s32_sss_noscc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; FAST: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1)
; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]]
; GREEDY-LABEL: name: usube_s32_sss_noscc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[TRUNC]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s1) = G_TRUNC %2
%4:_(s32), %5:_(s1) = G_USUBE %0, %1, %3
...