[GISel]: Add MachineIRBuilder support for passing in Flags while building instructions

[aditya_nandakumar]

Summary

Add the ability to pass in flags to buildInstr calls. Currently no validation is performed but that can be easily performed based on the opcode (if necessary).

[paquette]

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

797

The other instances of this have

Optional<unsigned> Flags = None

Should this also have that?

[aditya_nandakumar]

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

797

I believe default parameter values are only allowed only once during the declaration (it's done in MachineIRBuilder.h) .

[paquette]

LGTM

[aditya_nandakumar]

Submitted in r348893. Thanks for reviewing.

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
   ///      with the same (scalar or vector) type).
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
 
   MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_SUB \p Op0, \p Op1
   ///
   /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
   /// truncated to their width.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
   ///      with the same (scalar or vector) type).
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
 
   MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_MUL \p Op0, \p Op1
   ///
   /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
   /// truncated to their width.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
   ///      with the same (scalar or vector) type).
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
-                               const SrcOp &Src1) {
-    return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1});
+                               const SrcOp &Src1,
+                               Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
   }
 
   /// Build and insert \p Res = G_AND \p Op0, \p Op1
   ///
   /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
   /// Op1.
   ///
   /// \pre setBasicBlock or setMI must have been called.
public:
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
                               const SrcOp &Src1) {
     return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
   }
 
   virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
-                                         ArrayRef<SrcOp> SrcOps);
+                                         ArrayRef<SrcOp> SrcOps,
+                                         Optional<unsigned> Flags = None);
 };
 
 } // End namespace llvm.
 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

assert((TstTy.isScalar() ||
             (TstTy.isVector() &&
              TstTy.getNumElements() == Op0Ty.getNumElements())) &&
            "type mismatch");
 #endif
 }
 
 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
                                                  ArrayRef<DstOp> DstOps,
-                                                 ArrayRef<SrcOp> SrcOps) {
+                                                 ArrayRef<SrcOp> SrcOps,
+                                                 Optional<unsigned> Flags) {
   switch (Opc) {
   default:
     break;
   case TargetOpcode::G_SELECT: {
     assert(DstOps.size() == 1 && "Invalid select");
     assert(SrcOps.size() == 3 && "Invalid select");
     validateSelectOp(
         DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
   }
   }
 
   auto MIB = buildInstr(Opc);
   for (const DstOp &Op : DstOps)
     Op.addDefToMIB(*getMRI(), MIB);
   for (const SrcOp &Op : SrcOps)
     Op.addSrcToMIB(MIB);
+  if (Flags)
+    MIB->setFlags(*Flags);
   return MIB;
 }