[PPC64] Support R_PPC64_GOT16 Relocations

[martell]

Summary

When linking the linux kernel on ppc64
ld.lld: error: unrecognized reloc 58
58 is R_PPC64_GOT16_DS

[martell]

Tracking issue for clang built linux for @nickdesaulniers
https://github.com/ClangBuiltLinux/linux/issues/285

[martell]

I implemented this for ppc32 as well but there are a few things that need to be changed as a result of this so I will put that in a separate patch
I'm going to add a bunch of inline comments about things that could change.

[martell]

I'm probably going to learn something valuable about the global offsets table or the table of contents sections from the response to this :)

ELF/Arch/PPC64.cpp

23

Any suggestions on a rename here?
(It is no longer just toc but is got also)

63

Ditto

530

ditto

600

I don't think I can just optimize got relocations like toc relocations
but I'm not as familiar with the ISA / symbol groups as others.
Is a --got-optimize useful?

Take R_PPC64_ADDR16_HA for R_PPC64_GOT16_HA as an example

case R_PPC64_ADDR16_HA:
    if (Config->GotOptimize && IsGotRelType && ha(Val) == 0)
      writeInstrFromHalf16(Loc, 0x60000000);
    else
      write16(Loc, ha(Val));
    break;

606

comments probably need to change

[martell]

This was already implemented in rL349511 and rL349772.
Thanks @sfertile and sorry for the noise.
I don't know if there are any notes here that are useful. --got-optimize ?

[sfertile]

In D55498#1339415, @martell wrote:

This was already implemented in rL349511 and rL349772.
Thanks @sfertile and sorry for the noise.
I don't know if there are any notes here that are useful. --got-optimize ?

Hi @martell, Thanks for creating this patch. If I was aware of it I would have skipped mine and helped review this one. I've left a few comments below related to some of your comments.

ELF/Arch/PPC64.cpp

23

I think we should update this name possibly to PPC64TocBaseOffset or PPC64TocBaseBias . TOC/toc is somewhat overloaded in the ABI, a clearer name makes it explicit that this is an offset used in building the TocBase value.

63

I think this name is good as is. This calculates the address the toc pointer points at which is typically known as the tocbase.

67

This comment is out of date. I'm guessing this description is for the V1 abi. The V2 abi is unfortunately somewhat ambiguous on what exactly is and isn't contained in the Table-Of-Contents.

600

The optimization done here is strictly the transformation of a 2 instruction access sequence into a single instruction access sequence when the relocation offset fits in a single signed 16-bit immediate. It works similarly for got based relocation's as well as the toc based relocation (except it will work on the first 2 instructions of a 3 instruction got-indirect access sequence). For example a got-indirect access where the high-adjusted part of the access is zero gets transformed as such:

addis  r3, r2, sym@got@ha     --> nop
ld     r3, sym@got@l(r3)      --> ld r3, sym@got@l(r2)
lwa    r3, 0(r3)              --> lwa r3, 0(r3)

As for naming, gold does all these optimization with the --toc-optimize flag (likely because the optimization's are related to the toc-pointer )

ELF/Arch/PPC64.cpp

 
 using namespace llvm;
 using namespace llvm::object;
 using namespace llvm::support::endian;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 static uint64_t PPC64TocOffset = 0x8000;
 static uint64_t DynamicThreadPointerOffset = 0x8000;
 
 // The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
 // instructions that can be used as part of the initial exec TLS sequence.
 enum XFormOpcd {
   LBZX = 87,
   LHZX = 279,
   LWZX = 23,
enum DFormOpcd {
   STW = 36,
   STWU = 37,
   STFSU = 53,
   STFDU = 55,
   STD = 62,
   ADDI = 14
 };
 
 uint64_t elf::getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
   // the .got.
   uint64_t TocVA = In.Got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
   // thus permitting a full 64 Kbytes segment. Note that the glibc startup
   // code (crt1.o) assumes that you can get from the TOC base to the
   // start of the .toc section with only a single (signed) 16-bit relocation.
   return TocVA + PPC64TocOffset;
 }
default:
     llvm_unreachable("unknown relocation for IE to LE");
     break;
   }
 }
 
 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
                           const uint8_t *Loc) const {
   switch (Type) {
+  case R_PPC64_GOT16:
+  case R_PPC64_GOT16_DS:
+  case R_PPC64_GOT16_HA:
+  case R_PPC64_GOT16_HI:
+  case R_PPC64_GOT16_LO:
+  case R_PPC64_GOT16_LO_DS:
+    return R_GOT_OFF;
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
   case R_PPC64_TOC16_LO_DS:
     return R_GOTREL;
   case R_PPC64_TOC:
void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
                      unsigned RelOff) const {
   int32_t Offset = PltHeaderSize + Index * PltEntrySize;
   // bl __glink_PLTresolve
   write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
 }
 
 static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
   // Relocations relative to the toc-base need to be adjusted by the Toc offset.
   uint64_t TocBiasedVal = Val - PPC64TocOffset;
   // Relocations relative to dtv[dtpmod] need to be adjusted by the DTP offset.
   uint64_t DTPBiasedVal = Val - DynamicThreadPointerOffset;
 
   switch (Type) {
   // TOC biased relocation.
+  case R_PPC64_GOT16:
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSLD16:
   case R_PPC64_TOC16:
     return {R_PPC64_ADDR16, TocBiasedVal};
-  case R_PPC64_TOC16_DS:
+  case R_PPC64_GOT16_DS:
   case R_PPC64_GOT_TPREL16_DS:
   case R_PPC64_GOT_DTPREL16_DS:
+  case R_PPC64_TOC16_DS:
     return {R_PPC64_ADDR16_DS, TocBiasedVal};
+  case R_PPC64_GOT16_HA:
   case R_PPC64_GOT_TLSGD16_HA:
   case R_PPC64_GOT_TLSLD16_HA:
   case R_PPC64_GOT_TPREL16_HA:
   case R_PPC64_GOT_DTPREL16_HA:
   case R_PPC64_TOC16_HA:
     return {R_PPC64_ADDR16_HA, TocBiasedVal};
+  case R_PPC64_GOT16_HI:
   case R_PPC64_GOT_TLSGD16_HI:
   case R_PPC64_GOT_TLSLD16_HI:
   case R_PPC64_GOT_TPREL16_HI:
   case R_PPC64_GOT_DTPREL16_HI:
   case R_PPC64_TOC16_HI:
     return {R_PPC64_ADDR16_HI, TocBiasedVal};
+  case R_PPC64_GOT16_LO:
   case R_PPC64_GOT_TLSGD16_LO:
   case R_PPC64_GOT_TLSLD16_LO:
   case R_PPC64_TOC16_LO:
     return {R_PPC64_ADDR16_LO, TocBiasedVal};
-  case R_PPC64_TOC16_LO_DS:
+  case R_PPC64_GOT16_LO_DS:
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_DTPREL16_LO_DS:
+  case R_PPC64_TOC16_LO_DS:
     return {R_PPC64_ADDR16_LO_DS, TocBiasedVal};
 
   // Dynamic Thread pointer biased relocation types.
   case R_PPC64_DTPREL16:
     return {R_PPC64_ADDR16, DTPBiasedVal};
   case R_PPC64_DTPREL16_DS:
     return {R_PPC64_ADDR16_DS, DTPBiasedVal};
   case R_PPC64_DTPREL16_HA:
static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
   case R_PPC64_DTPREL64:
     return {R_PPC64_ADDR64, DTPBiasedVal};
 
   default:
     return {Type, Val};
   }
 }
 
 static bool isTocRelType(RelType Type) {
   return Type == R_PPC64_TOC16_HA || Type == R_PPC64_TOC16_LO_DS ||
          Type == R_PPC64_TOC16_LO;
 }
 
 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   // For a TOC-relative relocation, proceed in terms of the corresponding
   // ADDR16 relocation type.
   bool IsTocRelType = isTocRelType(Type);
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
   case R_PPC64_ADDR14: {
     checkAlignment(Loc, Val, 4, Type);
     // Preserve the AA/LK bits in the branch instruction