[PowerPC] VSX register support for inline assembly

[ZhangKang]

Summary

The patch is to add the VSX register support for inline assembly.

Before this patch, below case will get an error.

$ cat test.c
#include <altivec.h>
unsigned int a=0;
int main () {
  unsigned int *dbell=&a;
  int d;
 __asm__ __volatile__
                ("lxvw4x %%vs32, 0, %2\n\t"
                 "stxvw4x %%vs32, 0, %1"
                 : "=m"(*(volatile unsigned int*)(dbell)) 
                 : "r" (dbell),
                    "r" (&d)
                 : "vs32");  

  return 0;
}

Below is the error information.

$ clang -c test.c
t1.c:12:20: error: unknown register name 'vs32' in asm
                 : "vs32");  
                   ^
1 error generated.

After this patch, we can get inline assembly we expected without error.

[jsji]

I think we should override getGCCAddlRegNames to map vs* to reg numbers ,
this can avoid unnecessary renaming from vs32 to v0 in clobber list.

call void asm sideeffect "lxvw4x %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"(i32* %0, i32* %1, i32* %d) #1, !srcloc !3

[ZhangKang]

The old patch will rename from vs32 to` v0` in clobber list, that‘s is not very reasonable.
The new patch will override getGCCAddlRegNames to map vs* to reg numbers, this can avoid unnecessary renaming from vs32 to` v0` in clobber list.

[ZhangKang]

@jsji , I have uploaded a new patch to avoid renaming from vs32 to` v0` in clobber list.

[jsji]

RegNum are wrong!

clang/lib/Basic/Targets/PPC.cpp

416

RegNum is wrong here!
"vs0" should be mapped to RegNum of "f0", which is 33.
"vs32" should be mapped to RegNum of "v0", which is 78.

[ZhangKang]

Fix the VSX register index mappping of the array GCCAddlRegNames.

[ZhangKang]

@jsji I have updated a new patch for fix the error VSX register index mapping of the old patch.

clang/lib/Basic/Targets/PPC.cpp

416

I will learn it and check it, thanks for your point out my error.

416

Here, the value of AddlRegName is responding to the gcc macro ADDITIONAL_REGISTER_NAMES. In the array ADDITIONAL_REGISTER_NAMES, vs0~vs31 should be mapped to RegNum of f0~f31, which is 32~63. And vs32~vs63 should be mapped to RegNum of v0~v31, which is 77~108.

[ZhangKang]

clang/lib/Basic/Targets/PPC.cpp

416

Below is the ADDITIONAL_REGISTER_NAMES GCC manual said:

Macro: ADDITIONAL_REGISTER_NAMES

    If defined, a C initializer for an array of structures containing a name and a register number. This macro defines additional names for hard registers, thus allowing the asm option in declarations to refer to registers using alternate names.

[jsji]

LGTM. Thanks for fixing.

clang/lib/Basic/Targets/PPC.cpp

416

Yes, should be 32-63, 77-108. I forgot to use 0 as index start.

[nemanjai]

clang/lib/Basic/Targets/PPC.cpp

416

Is it possible to just not use magic numbers here at all? Do these correspond to something that is available in .td files? Is any of this possibly subject to change? Or if it is defined in some predefined macro/system header, etc. can we use the values from there?

[jsji]

clang/lib/Basic/Targets/PPC.cpp

416

This is fixed and defined in ABI, see ELFABIv2 "Table 2.26. Mappings of Common Registers".
AFAIK all ABIs use the same encoding.
Unfortunately, I don't think we have any td files or macros define these values.

@ZhangKang Please add a comment before this array,
so that it is easier to find doc about how these RegNum encoding are defined.

[ZhangKang]

clang/lib/Basic/Targets/PPC.cpp

416

If we don't use these numbers here, we can modify the array GCCRegAliases[] to add the map like {{"vs32"}, "v0"}, this method is my first patch for this pull-request. The first patch is in: https://reviews.llvm.org/D55192?id=176326
The first patch we use vs32 in inline-asm clobber list, we can see v0 in the IR clobber list not vs32. The lastest patch use GCCAddlRegNames, so we can see vs32 here.

I haven't found the correspond td files for these numbers. But these number of GCC ADDITIONAL_REGISTER_NAMES is same as DWARF Register Number Mapping. I think the GCC ADDITIONAL_REGISTER_NAMES is the PowerPC DWARF Register Number Mapping. So I think the numbes will not change for specify architecture, we can use these numbers.

You can found the DWARF Register Number Mapping in this website: http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#DW-REG . Also the DwarfEHRegSizeTable for PowerPC in clang is in: llvm/llvm/clang//lib/CodeGen/TargetInfo.cpp:4848~4893, this is the definitoin of PPC64_initDwarfEHRegSizeTable.

And I have checked the value of GCCAddlRegNames for SystemZ clang, its number also same as the SystemZ DWARF Register Number Mapping.

[ZhangKang]

Add the comment for the array AddlRegName to tell about how these RegNum encoding are defined.

[nemanjai]

I suppose since it is in the ABI, it is fine to leave the magic numbers there. And thanks for adding the comment. However, please verify that this mapping applies for ELF v1 as well and if it doesn't please add an appropriate guard.

[steven.zhang]

It seems that, there are more registers in ABI about the additional register than we present in this patch. It would be great if we would list all of them here or add some comments to indicate this at least.

[ZhangKang]

Because the ELFv1 is different with ELFv2, so I add the guard before use GCCAddlRegNames.

clang/lib/Basic/Targets/PPC.h

public:
 
   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
                          bool Enabled) const override;
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
+  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
+
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override {
     switch (*Name) {
     default:
       return false;
     case 'O': // Zero
       break;
     case 'b': // Base register

clang/lib/Basic/Targets/PPC.cpp

const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
     {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"},
     {{"cc"}, "cr0"},
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+const TargetInfo::AddlRegName GCCAddlRegNames[] = {
+    // Table of additional register names to use in user input.
+    {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35}, 
+    {{"vs4"}, 36},   {{"vs5"}, 37},   {{"vs6"}, 38},   {{"vs7"}, 39},
+    {{"vs8"}, 40},   {{"vs9"}, 41},   {{"vs10"}, 42},  {{"vs11"}, 43},
+    {{"vs12"}, 44},  {{"vs13"}, 45},  {{"vs14"}, 46},  {{"vs15"}, 47},
+    {{"vs16"}, 48},  {{"vs17"}, 49},  {{"vs18"}, 50},  {{"vs19"}, 51},
+    {{"vs20"}, 52},  {{"vs21"}, 53},  {{"vs22"}, 54},  {{"vs23"}, 55},
+    {{"vs24"}, 56},  {{"vs25"}, 57},  {{"vs26"}, 58},  {{"vs27"}, 59},
+    {{"vs28"}, 60},  {{"vs29"}, 61},  {{"vs30"}, 62},  {{"vs31"}, 63},
+    {{"vs32"}, 77},  {{"vs33"}, 78},  {{"vs34"}, 79},  {{"vs35"}, 80},
+    {{"vs36"}, 81},  {{"vs37"}, 82},  {{"vs38"}, 83},  {{"vs39"}, 84},
+    {{"vs40"}, 85},  {{"vs41"}, 86},  {{"vs42"}, 87},  {{"vs43"}, 88},
+    {{"vs44"}, 89},  {{"vs45"}, 90},  {{"vs46"}, 91},  {{"vs47"}, 92},
+    {{"vs48"}, 93},  {{"vs49"}, 94},  {{"vs50"}, 95},  {{"vs51"}, 96},
+    {{"vs52"}, 97},  {{"vs53"}, 98},  {{"vs54"}, 99},  {{"vs55"}, 100},
+    {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
+    {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
+};
+
+ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
+  return llvm::makeArrayRef(GCCAddlRegNames);
+}
+
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
     {"generic"}, {"440"},         {"450"},     {"601"},    {"602"},
     {"603"},     {"603e"},        {"603ev"},   {"604"},    {"604e"},
     {"620"},     {"630"},         {"g3"},      {"7400"},   {"g4"},
     {"7450"},    {"g4+"},         {"750"},     {"970"},    {"g5"},
     {"a2"},      {"a2q"},         {"e500mc"},  {"e5500"},  {"power3"},
     {"pwr3"},    {"power4"},      {"pwr4"},    {"power5"}, {"pwr5"},
     {"power5x"}, {"pwr5x"},       {"power6"},  {"pwr6"},   {"power6x"},

clang/test/CodeGen/inline-asm-matching-ppc-vsx.c

+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+// This case is to test VSX register support in the clobbers list for inline asm.
+void testVSX (void) {
+  unsigned int a = 0;
+  unsigned int *dbell=&a;
+  int d;
+  __asm__ __volatile__ (
+    "lxvw4x  %%vs32, 0, %2\n\t"
+    "stxvw4x %%vs32, 0, %1"
+    : "=m"(*(volatile unsigned int*)(dbell))
+    : "r" (dbell), "r" (&d)
+    : "vs32"
+  );
+}
+
+// CHECK: call void asm sideeffect "lxvw4x  %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"