I tried to make it generic but got real regression in ARM (tests 2007-05-09-tailmerge-2.ll and 2007-05-22-tailmerge-3.ll). The tail merge did not happen when expected. Turns out that is not unconditionally good regardless of the target.
sext would mean comparison with -1, not with 1 and does not really happen.
I do not think so. That is the final code produced:
s_and_b64 vcc, exec, s[12:13] s_cbranch_vccz BB0_4 ; %bb.3: ; %bb132 ; in Loop: Header=BB0_2 Depth=2 s_add_u32 s4, s8, s14 s_addc_u32 s5, s9, s15 s_branch BB0_5
As you may see we do not change exec here, just test it.
I do not need to kbow it, it can be anything producing i1. An i1 value will become sreg64 and will be directly used. In fact in the testcase it is not setcc, it is CopyFromReg.