[AMDGPU] Fold brcond (setcc zext(i1 x), 1, ne) -> brcond x

[arsenm]

Should this be a generic combine?

lib/Target/AMDGPU/SIISelLowering.cpp

8643

sext should also be OK

test/CodeGen/AMDGPU/dag-combine-brcond.ll

11

Can't this be reduced further?

[rampitec]

In D55030#1312124, @arsenm wrote:

Should this be a generic combine?

I tried to make it generic but got real regression in ARM (tests 2007-05-09-tailmerge-2.ll and 2007-05-22-tailmerge-3.ll). The tail merge did not happen when expected. Turns out that is not unconditionally good regardless of the target.

lib/Target/AMDGPU/SIISelLowering.cpp

8643

sext would mean comparison with -1, not with 1 and does not really happen.
I can add it, but it will complicate the code.

test/CodeGen/AMDGPU/dag-combine-brcond.ll

11

I do not think so. That is the final code produced:

        s_and_b64 vcc, exec, s[12:13]
        s_cbranch_vccz BB0_4
; %bb.3:                                ; %bb132
                                        ;   in Loop: Header=BB0_2 Depth=2
        s_add_u32 s4, s8, s14
        s_addc_u32 s5, s9, s15
        s_branch BB0_5

As you may see we do not change exec here, just test it.

[rampitec]

Added sext handling.

[mareko]

lib/Target/AMDGPU/SIISelLowering.cpp

8664

How do you know OrigCC is setcc? It could also be any bitwise op.

[rampitec]

lib/Target/AMDGPU/SIISelLowering.cpp

8664

I do not need to kbow it, it can be anything producing i1. An i1 value will become sreg64 and will be directly used. In fact in the testcase it is not setcc, it is CopyFromReg.

[rampitec]

It does not validate in some tests. I will investigate it as I do not see right away what is wrong.

[rampitec]

The error is that condition is actually has to be negated. However, if I just negate it it goes into an endless loop inside the combiner. I need to fix our BRCOND lowering instead.

lib/Target/AMDGPU/SIISelLowering.h

private:
   SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue performBrcondCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
   bool isLegalFlatAddressingMode(const AddrMode &AM) const;
   bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
   bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
 
   unsigned isCFIntrinsic(const SDNode *Intr) const;
 
   void createDebuggerPrologueStackObjects(MachineFunction &MF) const;

lib/Target/AMDGPU/SIISelLowering.cpp

#endif
   setTargetDAGCombine(ISD::XOR);
   setTargetDAGCombine(ISD::SINT_TO_FP);
   setTargetDAGCombine(ISD::UINT_TO_FP);
   setTargetDAGCombine(ISD::FCANONICALIZE);
   setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
   setTargetDAGCombine(ISD::ZERO_EXTEND);
   setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
+  setTargetDAGCombine(ISD::BRCOND);
 
   // All memory operations. Some folding on the pointer operand is done to help
   // matching the constant offsets in the addressing modes.
   setTargetDAGCombine(ISD::LOAD);
   setTargetDAGCombine(ISD::STORE);
   setTargetDAGCombine(ISD::ATOMIC_LOAD);
   setTargetDAGCombine(ISD::ATOMIC_STORE);
   setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
SDValue SITargetLowering::performClampCombine(SDNode *N,
   APFloat One(F.getSemantics(), "1.0");
   APFloat::cmpResult Cmp1 = F.compare(One);
   if (Cmp1 == APFloat::cmpGreaterThan)
     return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
 
   return SDValue(CSrc, 0);
 }
 
+SDValue SITargetLowering::performBrcondCombine(SDNode *N,
+                                               DAGCombinerInfo &DCI) const {
+  // Fold brcond (setcc zext(i1 x), 1, ne), label -> brcond x, label
+  SDValue CC = N->getOperand(1);
+  if (CC.getOpcode() != ISD::SETCC || !isa<ConstantSDNode>(CC.getOperand(1)))
+    return SDValue();
+
+  uint64_t CVal = CC.getConstantOperandVal(1);
+  ISD::CondCode Code = cast<CondCodeSDNode>(CC.getOperand(2))->get();
+  switch (CC.getOperand(0).getOpcode()) {
+  case ISD::ZERO_EXTEND:
+    if (!(CVal == 1 && Code == ISD::SETNE) &&
+        !(CVal == 0 && Code == ISD::SETEQ))
+      return SDValue();
+    break;
+  case ISD::SIGN_EXTEND:
+    if (!(CVal == (uint64_t)-1 && Code == ISD::SETNE) &&
+        !(CVal == 0 && Code == ISD::SETEQ))
+      return SDValue();
+    break;
+  default:
+    return SDValue();
+  }
+
+  SDValue OrigCC = CC.getOperand(0).getOperand(0);
+  if (OrigCC.getValueType() != MVT::i1)
+    return SDValue();
+
+  return DCI.DAG.getNode(ISD::BRCOND, SDLoc(N), MVT::Other, N->getOperand(0),
+                         OrigCC, N->getOperand(2));
+}
 
 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
                                             DAGCombinerInfo &DCI) const {
   if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
     return SDValue();
 
   switch (N->getOpcode()) {
   default:
case ISD::SCALAR_TO_VECTOR: {
     }
 
     break;
   }
   case ISD::EXTRACT_VECTOR_ELT:
     return performExtractVectorEltCombine(N, DCI);
   case ISD::INSERT_VECTOR_ELT:
     return performInsertVectorEltCombine(N, DCI);
+  case ISD::BRCOND:
+    return performBrcondCombine(N, DCI);
   }
   return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
 }
 
 /// Helper function for adjustWritemask
 static unsigned SubIdx2Lane(unsigned Idx) {
   switch (Idx) {
   default: return 0;

test/CodeGen/AMDGPU/dag-combine-brcond.ll

+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN: BB0_1:
+; GCN:   v_cmp_eq_u32_e64 [[CC:[^,]+]], s{{[0-9]+}}, 0
+; GCN: BB0_2:
+; GCN-NOT: v_cndmask_b32
+; GCN-NOT: v_cmp
+; GCN:   s_and_b64 vcc, exec, [[CC]]
+; GCN:   s_cbranch_vccz BB0_4
+define amdgpu_kernel void @test(float addrspace(1)* %arg1) {
+bb:
+  %tmp36 = getelementptr inbounds float, float addrspace(1)* %arg1, i64 undef
+  %tmp37 = getelementptr inbounds float, float addrspace(1)* %tmp36, i64 undef
+  br label %bb41
+
+bb40:                                             ; preds = %bb111
+  ret void
+
+bb41:                                             ; preds = %bb111, %bb
+  %tmp42 = phi i32 [ 0, %bb ], [ %tmp112, %bb111 ]
+  %tmp106 = icmp eq i32 %tmp42, 0
+  br label %bb114
+
+bb111:                                            ; preds = %bb150
+  %tmp112 = add nuw nsw i32 %tmp42, 1
+  %tmp113 = icmp eq i32 %tmp112, 32
+  br i1 %tmp113, label %bb40, label %bb41
+
+bb114:                                            ; preds = %bb150, %bb41
+  %tmp115 = phi i32 [ 0, %bb41 ], [ %tmp326, %bb150 ]
+  %tmp116 = shl i32 %tmp115, 5
+  %tmp122 = zext i32 %tmp116 to i64
+  %tmp123 = getelementptr inbounds float, float addrspace(1)* %tmp37, i64 %tmp122
+  br i1 %tmp106, label %bb125, label %bb132
+
+bb125:                                            ; preds = %bb114
+  %tmp128 = getelementptr inbounds float, float addrspace(1)* %tmp123, i64 16
+  %tmp129 = bitcast float addrspace(1)* %tmp128 to <4 x float> addrspace(1)*
+  br label %bb150
+
+bb132:                                            ; preds = %bb114
+  %tmp140 = getelementptr inbounds float, float addrspace(1)* %tmp123, i64 16
+  %tmp141 = bitcast float addrspace(1)* %tmp140 to <4 x float> addrspace(1)*
+  br label %bb150
+
+bb150:                                            ; preds = %bb132, %bb125
+  %tmp152 = phi <4 x float> addrspace(1)* [ %tmp129, %bb125 ], [ %tmp141, %bb132 ]
+  store <4 x float> zeroinitializer, <4 x float> addrspace(1)* %tmp152, align 16
+  %tmp326 = add nuw nsw i32 %tmp115, 2
+  %tmp327 = icmp eq i32 %tmp326, 32
+  br i1 %tmp327, label %bb111, label %bb114
+}

test/CodeGen/AMDGPU/multi-divergent-exit-region.ll

 
 ; GCN-LABEL: {{^}}uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value:
 ; GCN: s_cmp_gt_i32 s0, 1
 ; GCN: s_cbranch_scc0 [[FLOW:BB[0-9]+_[0-9]+]]
 
 ; GCN: v_cmp_ne_u32_e32 vcc, 7, v0
 
 ; GCN: {{^}}[[FLOW]]:
-; GCN: s_cbranch_vccnz [[FLOW1:BB[0-9]+]]
+; GCN: s_cbranch_execnz [[FLOW1:BB[0-9]+]]
 
 ; GCN: s_or_b64 exec, exec
 ; GCN: v_mov_b32_e32 v0, 2.0
 ; GCN-NOT: s_and_b64 exec, exec
 ; GCN: v_mov_b32_e32 v0, 1.0
 
 ; GCN: {{^BB[0-9]+_[0-9]+}}: ; %UnifiedReturnBlock
 ; GCN-NEXT: s_or_b64 exec, exec