Expand unavailable integer operations for vectors

[tlively]

Summary

Expands for vector types all of the integer operations that are
expanded for scalars because they are not supported at all by
WebAssembly.

This CL has no tests because such tests would really be testing the
target-independent expansion, but I'm happy to add tests if reviewers
think it would be helpful.

[aheejin]

Add [WebAssembly] to the CL header and commit message

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   }
 
   // Support saturating add for i8x16 and i16x8
   if (Subtarget->hasSIMD128())
     for (auto T : {MVT::v16i8, MVT::v8i16})
       for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
         setOperationAction(Op, T, Legal);
 
-  for (auto T : {MVT::i32, MVT::i64}) {
-    // Expand unavailable integer operations.
-    for (auto Op :
-         {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
-          ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
-          ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
+    for (auto T : {MVT::i32, MVT::i64}) {
+      setOperationAction(Op, T, Expand);
+    }
+    if (Subtarget->hasSIMD128()) {
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) {
         setOperationAction(Op, T, Expand);
       }
+      if (EnableUnimplementedWasmSIMDInstrs) {
+        setOperationAction(Op, MVT::v2i64, Expand);
+      }
+    }
   }
 
   // There is no i64x2.mul instruction
   setOperationAction(ISD::MUL, MVT::v2i64, Expand);
 
   // We have custom shuffle lowering to expose the shuffle mask
   if (Subtarget->hasSIMD128()) {
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {