[AArch64] Refactor the scheduling predicates (3/3) (NFC)

[evandro]

Summary

Refactor the scheduling predicates based on MCInstPredicate. In this case, AArch64InstrInfo::hasExtendedReg().

[andreadb]

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

78–83

You should just use a MCOpcodeSwitchStatement.

81

This should be:

def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;

[evandro]

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

78–83

Again, IsArithExtPred should be reused in an upcoming patch.

[andreadb]

LGTM. Thanks Evandro!

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
                                   AliasAnalysis *AA = nullptr) const override;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  /// Returns true if there is an extendable register and that the extending
-  /// value is non-zero.
-  static bool hasExtendedReg(const MachineInstr &MI);
-
   /// Does this instruction set its full destination register to zero?
   static bool isGPRZero(const MachineInstr &MI);
 
   /// Does this instruction rename a GPR without modifying bits?
   static bool isGPRCopy(const MachineInstr &MI);
 
   /// Does this instruction rename an FPR without modifying bits?
   static bool isFPRCopy(const MachineInstr &MI);

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addMemOperand(*MI.memoperands_begin());
   }
 
   MBB.erase(MI);
 
   return true;
 }
 
-/// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
-  default:
-    break;
-  case AArch64::ADDSWrx:
-  case AArch64::ADDSXrx:
-  case AArch64::ADDSXrx64:
-  case AArch64::ADDWrx:
-  case AArch64::ADDXrx:
-  case AArch64::ADDXrx64:
-  case AArch64::SUBSWrx:
-  case AArch64::SUBSXrx:
-  case AArch64::SUBSXrx64:
-  case AArch64::SUBWrx:
-  case AArch64::SUBXrx:
-  case AArch64::SUBXrx64:
-    if (MI.getOperand(3).isImm()) {
-      unsigned val = MI.getOperand(3).getImm();
-      return (val != 0);
-    }
-    break;
-  }
-
-  return false;
-}
-
 // Return true if this instruction simply sets its single destination register
 // to zero. This is equivalent to a register rename of the zero-register.
 bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     break;
   case AArch64::MOVZWi:
   case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

 }
 
 // Check for scaling in the register offset addressing mode.
 let FunctionMapper = "AArch64_AM::getMemDoShift" in
 def CheckMemScaled  : CheckImmOperandSimple<3>;
 
 // Generic predicates.
 
+// Identify arithmetic instructions with extend.
+def IsArithExtPred        : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64,
+                                         SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>;
+
 // Identify arithmetic instructions with shift.
 def IsArithShiftPred      : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
                                          SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
 
 // Identify logic instructions with shift.
 def IsLogicShiftPred      : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs,
                                          BICWrs, BICXrs, BICSWrs, BICSXrs,
                                          EONWrs, EONXrs,
def IsStoreRegOffsetPred  : CheckOpcode<[STRBBroW, STRBBroX,
                                          STRXroW, STRXroX,
                                          STRBroW, STRBroX,
                                          STRHroW, STRHroX,
                                          STRSroW, STRSroX,
                                          STRDroW, STRDroX]>;
 
 // Target predicates.
 
+// Identify arithmetic instructions with an extended register.
+def RegExtendedFn   : TIIPredicate<"hasExtendedReg",
+                                   MCOpcodeSwitchStatement<
+                                     [MCOpcodeSwitchCase<
+                                       IsArithExtPred.ValidOpcodes,
+                                       MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
+                                     MCReturnStatement<FalsePred>>>;
+def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
+
 // Identify arithmetic and logic instructions with a shifted register.
-def RegShiftedFn   : TIIPredicate<"hasShiftedReg",
+def RegShiftedFn    : TIIPredicate<"hasShiftedReg",
                                    MCOpcodeSwitchStatement<
                                      [MCOpcodeSwitchCase<
                                         !listconcat(IsArithShiftPred.ValidOpcodes,
                                                     IsLogicShiftPred.ValidOpcodes),
                                         MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
                                    MCReturnStatement<FalsePred>>>;
-def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
+def RegShiftedPred  : MCSchedPredicate<RegShiftedFn>;
 
 // Identify a load or store using the register offset addressing mode
 // with an extended or scaled register.
-def ScaledIdxFn    : TIIPredicate<"isScaledAddr",
+def ScaledIdxFn     : TIIPredicate<"isScaledAddr",
                                    MCOpcodeSwitchStatement<
                                      [MCOpcodeSwitchCase<
                                         !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
                                                     IsStoreRegOffsetPred.ValidOpcodes),
                                         MCReturnStatement<
                                           CheckAny<[CheckNot<CheckMemExtLSL>,
                                                     CheckMemScaled]>>>],
                                      MCReturnStatement<FalsePred>>>;
-def ScaledIdxPred  : MCSchedPredicate<ScaledIdxFn>;
+def ScaledIdxPred   : MCSchedPredicate<ScaledIdxFn>;

llvm/lib/Target/AArch64/AArch64Schedule.td

 def WriteST        : SchedWrite; // Store to base addr plus immediate offset
 def WriteSTP       : SchedWrite; // Store a register pair.
 def WriteAdr       : SchedWrite; // Address pre/post increment.
 
 def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
 def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
 
-// Predicate for determining when a extendedable register is extended.
-def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>;
-
 // Serialized two-level address load.
 // EXAMPLE: LOADGot
 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
 
 // Serialized two-level address lookup.
 // EXAMPLE: MOVaddr...
 def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;