[AArch64] Refactor the scheduling predicates (2/3) (NFC)

[evandro]

Summary

Refactor the scheduling predicates based on MCInstPredicate. In this case, AArch64InstrInfo::hasShiftedReg().

[andreadb]

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

74–79 ↗

(On Diff #174995)

Same as D54833 and D54777.

def RegShiftedPred : MCSchedPredicate<RegShiftedBody>;

You are inlining the entire body of hasShiftedReg here. You should replace it with this:

def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;

A TIIPredicate is a special kind of MCInstPredicate. See my other comment in D54777.

You should also rewrite RegShiftedFn so that it uses a more readable MCOpcodeSwitchStatement.

[evandro]

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

74–79 ↗

(On Diff #174995)

Again, I intend to reuse IsArithLogicShiftPred in another patch.

[andreadb]

Only a minor nit. Otherwise, it LGTM. Thanks!

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

43–44 ↗

(On Diff #175146)

Do you still need this? If not, then you can remove it.

[evandro]

llvm/lib/Target/AArch64/AArch64SchedPredicates.td

43–44 ↗

(On Diff #175146)

Will be using it shortly for Exynos.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h

public:
   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
                                   AliasAnalysis *AA = nullptr) const override;
 
   unsigned isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
-  /// Returns true if there is a shiftable register and that the shift value
-  /// is non-zero.
-  static bool hasShiftedReg(const MachineInstr &MI);
-
   /// Returns true if there is an extendable register and that the extending
   /// value is non-zero.
   static bool hasExtendedReg(const MachineInstr &MI);
 
   /// Does this instruction set its full destination register to zero?
   static bool isGPRZero(const MachineInstr &MI);
 
   /// Does this instruction rename a GPR without modifying bits?

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   }
 
   MBB.erase(MI);
 
   return true;
 }
 
 /// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
-  default:
-    break;
-  case AArch64::ADDSWrs:
-  case AArch64::ADDSXrs:
-  case AArch64::ADDWrs:
-  case AArch64::ADDXrs:
-  case AArch64::ANDSWrs:
-  case AArch64::ANDSXrs:
-  case AArch64::ANDWrs:
-  case AArch64::ANDXrs:
-  case AArch64::BICSWrs:
-  case AArch64::BICSXrs:
-  case AArch64::BICWrs:
-  case AArch64::BICXrs:
-  case AArch64::EONWrs:
-  case AArch64::EONXrs:
-  case AArch64::EORWrs:
-  case AArch64::EORXrs:
-  case AArch64::ORNWrs:
-  case AArch64::ORNXrs:
-  case AArch64::ORRWrs:
-  case AArch64::ORRXrs:
-  case AArch64::SUBSWrs:
-  case AArch64::SUBSXrs:
-  case AArch64::SUBWrs:
-  case AArch64::SUBXrs:
-    if (MI.getOperand(3).isImm()) {
-      unsigned val = MI.getOperand(3).getImm();
-      return (val != 0);
-    }
-    break;
-  }
-  return false;
-}
-
-/// Return true if this is this instruction has a non-zero immediate
 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     break;
   case AArch64::ADDSWrx:
   case AArch64::ADDSXrx:
   case AArch64::ADDSXrx64:
   case AArch64::ADDWrx:

llvm/trunk/lib/Target/AArch64/AArch64SchedPredicates.td

 }
 
 // Check for scaling in the register offset addressing mode.
 let FunctionMapper = "AArch64_AM::getMemDoShift" in
 def CheckMemScaled  : CheckImmOperandSimple<3>;
 
 // Generic predicates.
 
+// Identify arithmetic instructions with shift.
+def IsArithShiftPred      : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
+                                         SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
+
+// Identify logic instructions with shift.
+def IsLogicShiftPred      : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs,
+                                         BICWrs, BICXrs, BICSWrs, BICSXrs,
+                                         EONWrs, EONXrs,
+                                         EORWrs, EORXrs,
+                                         ORNWrs, ORNXrs,
+                                         ORRWrs, ORRXrs]>;
+
+// Identify arithmetic and logic instructions with shift.
+def IsArithLogicShiftPred : CheckAny<[IsArithShiftPred, IsLogicShiftPred]>;
+
 // Identify whether an instruction is a load
 // using the register offset addressing mode.
-def IsLoadRegOffsetPred  : CheckOpcode<[PRFMroW, PRFMroX,
+def IsLoadRegOffsetPred   : CheckOpcode<[PRFMroW, PRFMroX,
                                          LDRBBroW, LDRBBroX,
                                          LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX,
                                          LDRHHroW, LDRHHroX,
                                          LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX,
                                          LDRWroW, LDRWroX,
                                          LDRSWroW, LDRSWroX,
                                          LDRXroW, LDRXroX,
                                          LDRBroW, LDRBroX,
                                          LDRHroW, LDRHroX,
                                          LDRSroW, LDRSroX,
                                          LDRDroW, LDRDroX]>;
 
 // Identify whether an instruction is a load
 // using the register offset addressing mode.
-def IsStoreRegOffsetPred : CheckOpcode<[STRBBroW, STRBBroX,
+def IsStoreRegOffsetPred  : CheckOpcode<[STRBBroW, STRBBroX,
                                          STRHHroW, STRHHroX,
                                          STRWroW, STRWroX,
                                          STRXroW, STRXroX,
                                          STRBroW, STRBroX,
                                          STRHroW, STRHroX,
                                          STRSroW, STRSroX,
                                          STRDroW, STRDroX]>;
 
 // Target predicates.
 
+// Identify arithmetic and logic instructions with a shifted register.
+def RegShiftedFn   : TIIPredicate<"hasShiftedReg",
+                                  MCOpcodeSwitchStatement<
+                                    [MCOpcodeSwitchCase<
+                                       !listconcat(IsArithShiftPred.ValidOpcodes,
+                                                   IsLogicShiftPred.ValidOpcodes),
+                                       MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
+                                  MCReturnStatement<FalsePred>>>;
+def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
+
 // Identify a load or store using the register offset addressing mode
 // with an extended or scaled register.
-def ScaledIdxFn   : TIIPredicate<"isScaledAddr",
+def ScaledIdxFn    : TIIPredicate<"isScaledAddr",
                                   MCOpcodeSwitchStatement<
                                     [MCOpcodeSwitchCase<
                                        !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
                                                    IsStoreRegOffsetPred.ValidOpcodes),
                                        MCReturnStatement<
                                          CheckAny<[CheckNot<CheckMemExtLSL>,
                                                    CheckMemScaled]>>>],
                                     MCReturnStatement<FalsePred>>>;
-def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
+def ScaledIdxPred  : MCSchedPredicate<ScaledIdxFn>;

llvm/trunk/lib/Target/AArch64/AArch64Schedule.td

 def WriteST        : SchedWrite; // Store to base addr plus immediate offset
 def WriteSTP       : SchedWrite; // Store a register pair.
 def WriteAdr       : SchedWrite; // Address pre/post increment.
 
 def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
 def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
 
-// Predicate for determining when a shiftable register is shifted.
-def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>;
-
 // Predicate for determining when a extendedable register is extended.
 def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>;
 
 // Serialized two-level address load.
 // EXAMPLE: LOADGot
 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
 
 // Serialized two-level address lookup.

llvm/trunk/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s | FileCheck %s
 
   add x0, x1, x2, lsl #3
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      100
-# CHECK-NEXT: Total Cycles:      53
+# CHECK-NEXT: Total Cycles:      104
 # CHECK-NEXT: Total uOps:        100
 
 # CHECK:      Dispatch Width:    3
-# CHECK-NEXT: uOps Per Cycle:    1.89
-# CHECK-NEXT: IPC:               1.89
-# CHECK-NEXT: Block RThroughput: 0.5
+# CHECK-NEXT: uOps Per Cycle:    0.96
+# CHECK-NEXT: IPC:               0.96
+# CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      1     0.50                        add x0, x1, x2, lsl #3
+# CHECK-NEXT:  1      2     1.00                        add x0, x1, x2, lsl #3